TL16C754 Datasheet, PDF (13/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
functional description (continued)
Receiver: RXRDY becomes active when the trigger level has been reached OR when a timeout interrupt occurs.
It will go inactive when the FIFO is empty OR an error in the RX FIFO is flagged by LSR(7)
Figure 8 shows TXRDY and RXRDY in DMA mode 1.
wrptr
Trigger
Level
wrptr
TX
TXRDY
FIFO Full
TXRDY
Trigger
Level
rdptr
RX
RXRDY
At Least One
Location Filled
RXRDY
rdptr
FIFO Empty
Figure 8. TXRDY and RXRDY in DMA Mode 1
sleep mode
Sleep mode is an enhanced feature of the TL16C754 UART. It is enabled when EFR[4], the enhanced functions
bit, is set and when IER[4] is set. Sleep mode is entered when
– The serial data input line, RX, is idle (see break and time-out conditions).
– The TX FIFO and TX shift register are empty.
– There are no interrupts pending except THR and timeout interrupts.
Sleep mode will not be entered if there is data in the RX FIFO.
In sleep mode the UART clock and baud rate clock are stopped. Since most registers are clocked using these
clocks the power consumption is greatly reduced. The UART will wake up when any change is detected on the
RX line, when there is any change in the state of the modem input pins or if data is written to the TX FIFO.
NOTE:
Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done during sleep
mode. Therefore it is advisable to disable sleep mode using IER[4] before writing to DLL or DLH.
break and timeout conditions
An RX timeout condition is detected when the receiver line, RX, has been high for a time equivalent to (4X
programmed word length)+12 bits and there is at least one byte stored in the Rx FIFO.
When a break condition occurs, the TX line is pulled low. A break condition is activated by setting LCR[6].
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