TL16C754 Datasheet, PDF (24/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
Start
Bit
Data Bits (5–8)
Stop
Bit
TX (A–D)
D0 D1 D2 D3 D4 D5 D6 D7
5 Data Bits
6 Data Bits
7 Data Bits
Parity
Bit
IOW
Active
D0–D7
TXRDY (A–D)
TXRDY
Trigger
Level
T27d
T28d
Trigger
Level
Figure 21. Transmit Ready Timing in FIFO Mode
timing error condition
Texas Instruments has discovered a timing anomaly in TL16C754. This includes the TL16C754FN and
TL16C754PN as released devices.
The problem only occurs under a special set of circumstances, and can be worked around by using certain
timing descriped below. Depending on timing of actual system application, some customer may not see this
problem.
problem description
The second and/or third byte written into the transmit FIFO may be lost due to the timing condition described
below. The problem only occurs under specific boundary condition. That is:
D UART is operating in FIFO enabled mode.
D Total baud rate divisior, including divide-by-four through CLKSEL, is greater than or equal to four. If the
divide-by-one through CLKSEL is chosen and the baud rate divisor equals one, two, or three, no problem
will be seen.
D Exactly one byte is currently stored in transmit FIFO.
D Second write to a previously empty transmit FIFO occurs within a window T before the start of the SOUT
signal corresponding to the first character written to the transmit FIFO as illustrated in Figure 22. T is defined
as:
T = [(Divide-by factor^†) × (divisor in DLL, DLM) + 4] × XTAL1 clock cycle period
† _{Divide-by-factor can be selected by either the CLKSEL tie-off during reset or changing MCR[7] after reset. Refer to CLKSEL terminal definition}
on page 3 of data sheet for detail description.
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