TL16C754 Datasheet, PDF (12/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
functional description (continued)
Processor
IOW/IOR
LSR
IER
0000
THR
RHR
Figure 6. FIFO Polled Mode Operation
DMA signalling
There are two modes of DMA operation, DMA mode 0 or 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[0]=0) DMA occurs in single character transfers. In DMA mode 1
multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.
single DMA transfers (DMA mode0/FIFO disable)
Transmitter: When empty, the TXRDY signal becomes active. TXRDY will go inactive after one character has
been loaded into it.
Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the
receiver is empty.
Figure 7 shows TXRDY and RXRDY in DMA mode 0/FIFO disable.
TX
RX
TXRDY
RXRDY
wrptr
At Least One
Location Filled
rdptr
At Least One
Location Filled
TXRDY
RXRDY
wrptr
FIFO Empty
rdptr
FIFO Empty
Figure 7. TXRDY and RXRDY in DMA Mode 0/FIFO Disable
block DMA transfers (DMA mode 1)
Transmitter: TXRDY is active when a trigger level number of spaces are available. It becomes inactive when
the FIFO is full.
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