TL16C754 Datasheet, PDF (34/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
PRINCIPLES OF OPERATION
divisor latches (DLL, DLH)
These are two 8-bit registers, which store the 16-bit divisor for generation of the baud clock in the baud rate
generator. DLH, stores the most significant part of the divisor. DLL stores the least significant part of the division.
DLL and DLH can only be written to before sleep mode is enabled (i.e., before IER[4] is set).
transmission control register (TCR)
This 8-bit register is used to store the receive FIFO threshold levels to start/stop transmission during
hardware/software flow control. Table 18 shows transmission control register bit settings.
Table 18. Transmission Control Register (TCR) Bit Settings
BIT NO.
3:0
7:4
BIT SETTINGS
RCV FIFO trigger level to HALT transmission (0–60)
RCV FIFO trigger level to RESTORE transmission (0–60)
TCR trigger levels are available from 0–60 bytes with a granularity of four.
TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer must program the TCR such
that TCR[3:0] > TCR[7:4]. There is no built-in hardware check to make sure this condition is met. Also, the TCR
must be programmed with this condition before Auto-RTS or software flow control is enabled to avoid spurious
operation of the device.
trigger level register (TLR)
This 8-bit register is used to store the transmit and received FIFO trigger levels used for DMA and interrupt
generation. Trigger levels from 4–60 can be programmed with a granularity of 4. Table 19 shows trigger level
register bit settings.
Table 19. Trigger Level Register (TLR) Bit Settings
BIT NO.
3:0
7:4
BIT SETTINGS
Transmit FIFO trigger levels (4–60), number of spaces available
RCV FIFO trigger levels (4–60), number of characters available
TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or TLR[7:4] are zero, then the selectable
trigger levels via the FIFO control register (FCR) are used for the transmit and receive FIFO trigger levels.
Trigger levels from 4–60 bytes are available with a granularity of four. The TLR should be programmed for N/4,
where N is the desired trigger level.
FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs. Table 20 shows the FIFO
ready register bit settings.
Table 20. FIFO Ready Register
BIT NO.
3:0
7:4
BIT SETTINGS
0 = There are less than a TX trigger level number of spaces available in the TX FIFO.
1 = There are at least a TX trigger level number of spaces available in the TX FIFO
0 = There are less than a RX trigger level number of characters in the RX FIFO.
1 = The RX FIFO has more than a RX trigger level number of characters available for reading OR a timeout condition has occurred.
The FIFORdy register is a read only register and can be accessed when any of the four UARTs are selected
CAS A-D = 0, MCR[2] (FIFORdy Enable) is a 1 and loopback is disabled. Its address space is 111.
34
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265