TL16C754 Datasheet, PDF (27/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO

TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
PRINCIPLES OF OPERATION
register map^†
Each register is selected using address lines A[0], A[1], A[2] and, in some cases, bits from other registers. The
programming combinations for register selection are shown in Table 7.
Table 7. Register Map – Read/Write Properties
A[2] A[1] A[0]
READ MODE
0
0
0 Receive holding register (RHR)
0
0
1 Interrupt enable register (IER)
0
1
0 Interrupt identification register (IIR)
0
1
1 Line control register (LCR)
1
0
0 Modem control register (MCR)
1
0
1 Line status register (LSR)
1
1
0 Modem status register (MSR)
1
1
1 Scratch register (SPR)
WRITE MODE
Transmit holding register (THR)
Interrupt enable register
FIFO control register (FCR)
Line control register
Modem control register
Scratch register (SPR)
0
0
0 Divisor latch LSB (DLL)
0
0
1 Divisor latch MSB (DLH)
0
1
0 Enhanced feature register (EFR)
1
0
0 Xon-1 word
1
0
1 Xon-2 word
1
1
0 Xoff-1 word
1
1
1 Xoff-2 word
1
1
0 Transmission control register (TCR)
1
1
1 Trigger level register (TLR)
Divisor latch LSB (DLL)
Divisor latch MSB (DLH
Enhanced feature register
Xon-1 word
Xon-2 word
Xoff-1 word
Xoff-2 word
Transmission control register
Trigger level register
1
1
1 FIFO ready register
† _{DLL and DLH are accessible only when LCR bit-7 is 1.}
Enhanced feature register, Xon1, 2 and Xoff1, 2 are accessible only when LCR is set to 10111111 (8hBF).
Transmission control register and trigger level register are accessible only when EFR[4] = 1 and MCR[6] = 1, i.e.. EFR[4] and MCR[6] are
read/write enables.
FCR FIFORdy register is accessible when any CS A-D = 0, MCR [2] = 1 and loopback MCR [4] = 0 is disabled.
MCR[7] can only be modified when EFR[4] is set.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
27