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TL16C754 Datasheet, PDF (10/39 Pages) Texas Instruments – QUAD UART WITH 64-BYTE FIFO
TL16C754
QUAD UART WITH 64-BYTE FIFO
SLLS279A – OCTOBER 1998 – REVISED OCTOBER 1999
functional description (continued)
reset
Table 2 summarizes the state of registers after reset.
Table 2. Register Reset Functions
REGISTER
RESET
CONTROL
RESET STATE
Interrupt enable register
Interrupt identification register
FIFO control register
Line control register
Modem control register
RESET
RESET
RESET
RESET
RESET
All bits cleared
Bit 0 is set. All other bits cleared.
All bits cleared
Reset to 00011101 (1D hex).
Bit 6–0 cleared. Bit 7 reflects the inverse of
the CLKSEL pin value.
Line status register
Modem status register
Enhanced feature register
RESET
RESET
RESET
Bits 5 and 6 set. All other bits cleared.
Bits 0–3 cleared. Bits 4–7 input signals.
Bit 6 – 0 is cleared. Bit 7 reflects the inverse
of the CLKSEL pin value.
Receiver holding register
RESET
Pointer logic cleared
Transmitter holding register
RESET
Pointer logic cleared
Transmission control register
RESET
All bits cleared
Trigger level register
RESET
All bits cleared
NOTE: Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal
RESET, i.e., they hold their initialization values during reset.
Table 3 summarizes the state of some signals after reset.
Table 3. Signal Reset Functions
SIGNAL
TX
RTS
DTR
RXRDY
TXRDY
RESET
CONTROL
RESET
RESET
RESET
RESET
RESET
RESET STATE
High
High
High
High
Low
interrupts
The TL16C754 UART has interrupt generation and prioritization (6 prioritized levels of interrupts) capability. The
interrupt enable register (IER) enables each of the 6 types of interrupts and the INT signal in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0–3, 5–7. When an interrupt
is generated, the interrupt identification register(IIR) indicates that an interrupt is pending and provides the type
of interrupt through IIR[5–0]. Table 4 summarizes the interrupt control functions.
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