DS100DF410 Datasheet, PDF (4/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
www.ti.com
Pin Descriptions
Pin Name
Pin #
I/O, Type⁽¹⁾
Description
HIGH-SPEED DIFFERENTIAL I/O
RXP0
RXN0
1
I, CML
Inverting and non-inverting CML-compatible differential inputs to the equalizer.
2
Nominal differential input impedance = 100Ω.
RXP1
RXN1
4
I, CML
Inverting and non-inverting CML-compatible differential inputs to the equalizer.
5
Nominal differential input impedance = 100Ω.
RXP2
RXN2
8
I, CML
Inverting and non-inverting CML-compatible differential inputs to the equalizer.
9
Nominal differential input impedance = 100Ω.
RXP3
RXN3
11
I, CML
Inverting and non-inverting CML-compatible differential inputs to the equalizer.
12
Nominal differential input impedance = 100Ω.
TXP0
TXN0
36
O, CML
Inverting and non-inverting CML-compatible differential outputs from the driver.
35
Nominal differential output impedance = 100Ω.
TXP1
TXN1
33
O, CML
Inverting and non-inverting CML-compatible differential outputs from the driver.
32
Nominal differential output impedance = 100Ω.
TXP2
TXN2
29
O, CML
Inverting and non-inverting CML-compatible differential outputs from the driver.
28
Nominal differential output impedance = 100Ω.
TXP3
TXN3
26
O, CML
Inverting and non-inverting CML-compatible differential outputs from the driver.
25
Nominal differential output impedance = 100Ω.
LOOP FILTER CONNECTION PINS
LPF_CP_0
LPF_REF_0
47
I/O, analog Loop filter connection
48
Place a 22 nF ± 10% Capacitor between LPF_CP_0 and LPF_REF_0
LPF_CP_1
LPF_REF_1
38
I/O, analog Loop filter connection
37
Place a 22 nF ± 10% Capacitor between LPF_CP_1 and LPF_REF_1
LPF_CP_2
LPF_REF_2
23
I/O, analog Loop filter connection
24
Place a 22 nF ± 10% Capacitor between LPF_CP_2 and LPF_REF_2
LPF_CP_3
LPF_REF_3
14
I/O, analog Loop filter connection
13
Place a 22 nF ± 10% Capacitor between LPF_CP_3 and LPF_REF_3
REFERENCE CLOCK I/O
REFCLK_IN
19
I, 2.5V analog Input is 2.5 V, 25 MHz ± 100 ppm reference clock from external oscillator
No stringent phase noise requirement
REFCLK_OUT
42
O, 2.5V analog Output is 2.5 V, buffered replica of reference clock input for connecting multiple
DS100DF410s on a board
LOCK INDICATOR PINS
LOCK_0
LOCK_1
LOCK_2
LOCK_3
45
O, 2.5V
Output is 2.5 V, the pin is high when CDR lock is attained on the corresponding
40
LVCMOS channel
21
Note that these pins are shared with SMBus address strap input functions read
16
at startup.
SMBus MASTER MODE PINS
ALL_DONE
41
O, 2.5V
Output is 2.5 V, the pin goes low to indicate that the SMBus master EEPROM
LVCMOS read has been completed.
READ_EN
44
I, 2.5V
Input is 2.5 V, a transition from high to low starts the load from the external
LVCMOS EEPROM. The READ_EN pin must be tied low when in SMBus slave mode
INTERRUPT OUTPUT
INT
43
O, 3.3V
Used to signal horizontal or vertical eye opening out of tolerance, loss of signal
LVCMOS, Open detect, or CDR unlock
Drain
External 2KΩ to 5KΩ pull-up resistor is required.
Pin is 3.3 V LVCMOS tolerant.
SERIAL MANAGEMENT BUS (SMBus) INTERFACE
EN_SMB
20
I, 2.5V analog Input is 2.5 V, selects SMBus master mode or SMBus slave mode
EN_SMB = High for slave mode
EN_SMB = Float for master mode
Tie READ_EN pin low for SMBus slave mode. See Table 1
(1) Notes:
I = Input, O = Output and 2.5V LVCMOS pins are 2.5 V levels only.
Only SMBus pins SDA and SDC and INT pin are 3.3 V tolerant. These three pins are open-drain and require external pull-up
resistors.
4
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