DS100DF410 Datasheet, PDF (12/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
DEVICE CONFIGURATION INFORMATION
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The DS100DF410 can be configured by the user to optimize its operation. The four channels can be optimized
independently in SMBus master or SMBus slave mode. The operational settings available for user configuration
include the following.
• CTLE boost setting
• DFE tap weight and polarity setting
• Driver output voltage
• Driver output de-emphasis
• Driver output rise/fall time
Configuration of the DS100DF410 is accomplished by writing the appropriate values into various device registers
over the SMBus. This can either be done while the device is operating or upon initial power-up. When the
DS100DF410 is operating it behaves like an SMBus slave device, and its register contents can be read or written
over the SMBus. Optionally, when the DS100DF410 first powers up, it can behave like an SMBus master and
read its register contents autonomously from an external EEPROM.
CTLE Boost Setting
The CTLE is a four-stage amplifier with an adjustable, quasi-high-pass transfer function on each stage. The
overall frequency response of the CTLE is set by adjusting the boost of each stage independently. Each stage of
the CTLE can be set to one of four boost settings. The amount of high-frequency boost supplied by each stage
generally increases with increasing boost settings.
The CTLE can also be configured to adapt automatically to provide the optimum boost level for its input signal.
Automatic adaptation of the CTLE only is the default mode of operation for the DS100DF410.
DFE Tap Weight and Polarity Setting
The DS100DF410 includes a five-tap decision-feedback equalizer (DFE) which operates on the signal at the
output of the CTLE.
When the tap weights and polarities are properly set, the DFE approximates a matched filter for the input
transmission channel frequency response as modified by the CTLE frequency response. The CTLE and the DFE
work together to compensate for the input transmission channel response.
The DFE discriminates against input noise and random jitter as well as against crosstalk at the input to the
DS100DF410. When the DFE tap weights and polarities are properly set the DS100DF410 CDR operates at an
acceptable BER with more severe channel impairments than can be compensated with the CTLE alone.
It is possible to automatically or manually set the tap weights and polarities in the DS100DF410. Determining the
correct tap weights manually is difficult and time-consuming. The DS100DF410 automatically adapts the DFE tap
weights and polarities in normal operation. This automatic adaptation provides superior BER performance for
noisy channels and channels subject to crosstalk aggressors.
The DFE is powered down by default. In order for the DFE tap weights and polarities to be applied to the input
signal, bit 3 of register 0x1e, the dfe_PD bit, should be set to 0 to power up the DFE. Also the adapt mode
setting in register 0x31, bits[6:5] should be set to 2b'10 or 2b'11 so the device can automatically adapt the CTLE
and DFE.
Driver Output Voltage
The differential output voltage of the DS100DF410 can be configured from a nominal setting of 600 mV peak-to-
peak differential to a nominal setting of 1.3 V peak-to-peak differential, depending upon the application. The
driver output voltage as set is the typical peak-to-peak differential output voltage with no de-emphasis enabled.
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