DS100DF410 Datasheet, PDF (35/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
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SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
such as cables and simple PCB traces.
• Mode 2: In this mode, both the CTLE and the DFE are adapted to compensate for additional loss, reflections,
and crosstalk in the input transmission channel.
– The maximum DFE tap weights can be constrained using register 0x34, bits 3:0, and register 0x35, bits
4:0 as shown in Table 5.
• Mode 3: In this mode, both the CTLE and DFE are adapted as in mode 2. However, in mode 3, more
emphasis is placed on the DFE setting. This mode may give better results for high crosstalk transmission
channels.
Bits 6:5 of register 0x31 determine the adaptation mode to be used. The mapping of these register bits to the
adaptation algorithm is shown in Table 5.
Register 0x31, Bit 6
adapt_mode[1]
0
0
1
1
Table 11. DS100DF410 Adaptation Algorithm Settings
Register 0x31, Bit 5
adapt_mode[0]
0
1
0
1
Adapt Mode Setting <1:0>
00
01
10
11
Adaptation Algorithm
No Adaptation
Adapt CTLE Until Optimum
(Default)
Adapt CTLE Until Optimum then
DFE, then CTLE Again
Adapt CTLE Until Lock, then
DFE, the CTLE Again
By default the DS100DF410 requires that the equalized internal eye exhibit horizontal and vertical eye openings
greater than a pre-set minimum in order to declare a successful lock. The minimum values are set in register
0x6a.
The DS100DF410 continuously monitors the horizontal and vertical eye openings while it is in lock. If the eye
opening falls below the threshold set in register 0x6a, the DS100DF410 will declare a loss of lock.
The continuous monitoring of the horizontal and vertical eye openings may be disabled by clearing bit 7 of
register 0x3e.
Initiating Adaptation
Register 0x24, bit 2, and Register 0x2f, bit 0
When the DS100DF410 becomes unlocked, it will automatically try to acquire lock. If an adaptation mode is
selected using bits 6:5 in register 0x31, the DS100DF410 will also try to adapt its CTLE and its DFE.
Adaptation can also be initiated by the user. CTLE adaptation can be initiated by setting and then clearing
register 0x2f, bit 0. DFE adaptation can be initiated by setting and then clearing bit 2 of register 0x24.
Setting the Reference Enable Mode
Register 0x36, bits 5:4
Register 0x36, bits 5:4, are the ref_mode<1:0> bits. These bits should be set to a value of 2'b11. Note that this is
not the default. The reference mode must be set prior to using the DS100DF410.
A 25 MHz reference clock signal must be provided on the reference in pin (pin 19). The use of the reference
clock in the DS100DF410 is explained below.
First, the reference clock allows the DS100DF410 to calibrate its VCO frequency at power-up and upon reset.
This enables the DS100DF410 to determine the optimum coarse VCO tuning setting a-priori, which makes phase
lock much faster. The DS100DF410 is not required to tune through the available coarse VCO tuning settings as it
tries to acquire lock to an input signal. It can select the correct setting immediately.
Second, if the DS100DF410 loses lock for some reason and the VCO drifts from its phase-locked frequency, the
DS1010DF410 can detect this very quickly using the reference clock. Detecting an out-of-lock condition quickly
allows the DS100DF410 to raise an interrupt indicating that it has lost lock quickly, which the system controller
can then service to correct the problem quickly.
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