DS100DF410 Datasheet, PDF (30/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
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In normal operation, the DS100DF410 will determine the required VCO divider ratio automatically. The most
common application for overriding the divider ratio is when the VCO is set to free-run. Normally the divider ratio
should not be overridden except in this case.
Using the PRBS Generator
Register 0x0d, bit 5, Register 0x1e, bit 4, and Register 0x30, bit 3 and bits 1:0
The DS100DF410 includes an internal PRBS generator which can generate standard PRBS-9 and PRBS-31 bit
sequences. The PRBS generator can produce a PRBS sequence that is synchronous to the incoming data
signal, or it can generate a PRBS sequence using the internal free-running VCO as a clock. Both modes of
operation are described in the paragraphs that follow.
To produce a PRBS sequence that is synchronized to the incoming data signal, the DS100DF410 must be
locked to the incoming signal. When this is true, the signal detect is set and the channel is active. In addition, the
VCO is locked to the incoming signal The VCO will remain locked to the incoming signal regardless of the state
of the output multiplexer.
To activate the PRBS generator, first set bit 4 of register 0x1e. This bit enables the PRBS generator digital
circuitry. Then reset the PRBS clock by clearing bit 3 of register 0x30. Select either PRBS-9 or PRBS-31 by
setting bits 1:0 of register 0x30. Set this bit field to 0x0 for PRBS-9 and to 0x2 for PRBS-31. Then load the PRBS
clock by setting bit 3 of register 0x30. Finally, enable the PRBS clock by setting bit 5 of register 0x0d. This
sequence of register writes will enable the internal PRBS generator.
As described above, to select the PRBS generator as the output for the selected channel, set bit 5 of register
0x09, the output multiplexer override. Then write 0x4 to bits 7:5 of register 0x1e. This selects the PRBS
generator for output.
For the case described above, the output PRBS sequence will be synchronous to the incoming data. There are
two other cases of interest. The first is when there is an input signal but the PRBS sequence should not be
synchronous to it. In other words, in this case it is desired that the VCO should free-run. The second case is
when there is no input signal, but the PRBS sequence should still be output. Again, in this case, the VCO is free-
running.
The register settings for these two cases are almost the same. The only difference is that, if there is no input
signal, then the channel will be disabled and powered-down by default. In order to force enable the channel,
write a 1 to bit 7 and a 0 to bit 6 of register 0x14. This forces the signal detect to be active and enables the
selected channel.
The remainder of the register write sequence is designed to disable the phase-locked loop so that the VCO can
free run.
First write a 1 to bit 3 of register 0x09, then 0x0 to bits 1:0 of register 0x1b. This disables the charge pump for
the phase-locked loop.
Next write a 1 to bit 2 of register 0x09. This enables the VCO divider override. Then set the VCO divider ratio by
writing to register 0x18 as shown in Table 8. For an output frequency of approximately 10.3125 GHz, set the
divider ratio to 1 by writing 0x0 to bits 6:4 of register 0x18. Do not clear bit 3 when you write a 1 to bit 2 of
register 0x09.
Now write a 1 to bit 7 of register 0x09. This enables the VCO CAP DAC override. Write the desired VCO cap
count to register 0x08, bits 4:0. The mapping of VCO frequencies to cap count will vary somewhat from part to
part. The VCO cap count should be set to 0x0c to yield an output VCO frequency of approximately 10.3125 GHz.
Do not clear bits 3 and 2 when you write a 1 to bit 7 of register 0x09.
Now write a 1 to bit 6 of register 0x09. This enables the VCO LPF DAC which can generate a VCO control
voltage internally to the DS100DF410. Once the LPF DAC is enabled, write the desired value of the LPF DAC
output in register 0x1f, bits 4:0. For an output VCO frequency of approximately 10.3125 GHz, set the LPF DAC
setting to 0x12. Do not clear the remaining bits of register 0x09 when you write a 1 to bit 6.
Now, as above, enable the PRBS generator and set it to the desired bit sequence, then select the output to be
the PRBS generator by setting the output multiplexer. Notice that when this entire sequence has been
completed, bits 7:2 of register 0x09 will all be set. The default value of register 0x09 is 0x00, so you can clear all
the overrides when you are ready to return to normal operation by writing 0x00 to register 0x09.
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