DS100DF410 Datasheet, PDF (16/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
From External
SMBus Master
SDA
SDC
EEPROM
DS100DF410
DS100DF410
One or both of these lines should
float for an EEPROM larger than
256 bytes
Set to unique
SMBus
address
Set to unique
SMBus
address
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DS100DF410
DS100DF410
DS100DF410
Set to unique
SMBus
address
Set to unique
SMBus
address
Set to unique
SMBus
address
Figure 3. Connection Diagram for Multiple DS100DF410s in SMBus Master Mode
In SMBus master mode after the DS100DF410 has finished reading its initial configuration from the external
EEPROM it reverts to SMBus slave mode. In either mode the SMBus data and clock lines, SDA and SDC, are
used. Also, in either mode, the SMBus address is latched in on the address strap lines on power-up. In SMBus
slave mode, if the READ_EN pin is not tied low, the DS100DF410 will not latch in the address on its address
strap lines. It will instead latch in an SMBus write address of 0x30 regardless of the state of the address strap
lines. This is a test feature. Obviously a system with multiple retimers cannot operate properly if all the retimers
are responding to the same SMBus address. Tie the READ_EN pin low when operating in SMBus slave mode to
avoid this condition.
The DS100DF410 reads its SMBus address upon power-up from the SMBus address lines.
Address Lines <ADDR_[3:0]>
In either SMBus master or SMBus slave mode the DS100DF410 must be assigned an SMBus address. A unique
address must be assigned to each device on the SMBus.
The SMBus address is latched into the DS100DF410 on power-up. The address is read in from the state of the
<ADDR_[3:0]> lines (pins 16, 21, 40, and 45 respectively) upon power-up. In either SMBus mode these address
lines are input pins on power-up.
16
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