DS100DF410 Datasheet, PDF (10/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
www.ti.com
The CTLE is a four-stage variable boost high-gain amplifier with a quasi-high-pass characteristic. Each of the
four stages can be set to provide various amounts of high-frequency boost with the overall transfer function of
the CTLE set by the cascade of all four sections. The high-frequency boost of each CTLE stage is variable. The
optimum boost for each stage is one that causes the transfer function magnitude of the transmission channel and
the CTLE in cascade to be flat over a band of frequencies extending up to half the data rate which is commonly
referred to as the “Nyquist” frequency. In normal operation, the DS100DF410 sets the boost of the CTLE
automatically to approximate the optimum cascaded response.
In addition to the CTLE, the DS100DF410 includes a clock-based Decision-Feedback Equalizer or DFE. The
DFE operates as a symbol-spaced, discrete-time, nonlinear analog filter which provides additional discrimination
against signal impairments, both those arising from the dispersive transmission channel between the transmitter
and the DS100DF410 and those arising from noise in the system and crosstalk between transmission channels.
The DFE introduces an analog summing node between the CTLE output and the comparator, which makes the
“decision” whether the current bit is a 1 or a 0. At this summing node scaled versions of the previous five
decision results (bits) are added in an analog fashion to the input signal at the summing node, and the output of
the summing node is the input to the comparator. This is a well-known type of discrete-time nonlinear adaptive
filter.
The scaling or tap weight and the algebraic sign of each of the five taps of the DFE are variable. In normal
operation the DS100DF410 sets the tap weights and polarities automatically to approximate the optimum noise-
and crosstalk-free response.
Clock and Data Recovery
The DS100DF410 performs its clock and data recovery function by detecting the bit transitions in the incoming
data stream and locking its internal VCO to the clock represented by the mean arrival times of these bit
transitions. This process produces a recovered clock with jitter which is greatly reduced for jitter frequencies
outside the bandwidth of the CDR Phase-Locked Loop (PLL). This is the primary benefit of using the
DS100DF410 in a system. It significantly reduces the jitter present in the data stream, in effect resetting the jitter
budget for the system.
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