DS100DF410 Datasheet, PDF (20/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
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Device Revision and Device ID
Register 0x01
Control/shared register 0x01 contains the device revision and device ID. The device revision shown in Table 3 is
the current revision for the DS100DF410. The device ID will be different for the different devices in the retimer
family. The value shown in "For the DS100DF410, Register 0x01, bits 4:0 = 0x10" is the correct value for the
DS100DF410. This register is useful because it can be interrogated by software to determine the device variant
and revision installed in a particular system. The software might then configure the device with appropriate
settings depending upon the device variant and revision.
Control/Shared Register Reset
Register 0x04, bit 6
Register 0x04, bit 6, clears all the control/shared registers back to their factory defaults. This bit is self-clearing,
so it is cleared after it is written and the control/shared registers are reset to their factory default values.
Interrupt Channel Flag Bits
Register 0x05, bits 3:0
The operation of these bits is described in the section on interrupt handling later in this data sheet.
SMBus Master Mode Control Bits
Register 0x04, bits 5 and 4 and register 0x05, bits 7 and 4
Register 0x04, bit 5, can be used to reset the SMBus master mode. This bit should not be set if the
DS100DF410 is in SMBus slave mode. This is an undefined condition.
When this bit is set, if the EN_SMB pin is floating (meaning that the DS100DF410 is in SMBus master mode),
then the DS100DF410 will read the contents of the external EEPROM when the READ_EN pin is pulled low. This
bit is not self-clearing, so it should be cleared after it is set.
When the DS100DF410 EN_SMB pin is floating (meaning that the DS100DF410 is in SMBus master mode), it
will read from its external EEPROM when its READ_EN pin goes low. After the EEPROM read operation is
complete, register 0x05, bit 4 will be set. Alternatively, the DS100DF410 will read from its external EEPROM
when triggered by register 0x04, bit 4, as described below.
When register 0x04, bit 4, is set, the DS100DF410 reads its configuration from an external EEPROM over the
SMBus immediately. When this bit is set, the DS100DF410 does not wait until the READ_EN pin is pulled low to
read from the EEPROM. This EEPROM read occurs whether the DS100DF410 is in SMBus master mode or not.
If the read from the EEPROM is not successful, for example because there is no EEPROM present, then the
DS100DF410 may hang up and a power-up reset may be necessary to return it to proper operation. You should
only set this bit if you know that the EEPROM is present and properly configured.
If the EEPROM read has already completed, then setting register 0x04, bit 4, will not have any effect. To cause
the DS100DF410 to read from the EEPROM again it is necessary to set bit 5 of register 0x04, resetting the
SMBus master mode. If the DS100DF410 is not in SMBus master mode, do not set this bit. After setting this bit,
it should be cleared before further SMBus operations.
After SMBus master mode has been reset, the EEPROM read may be initiated either by pulling the READ_EN
pin low or by then setting register 0x04, bit 4.
Register 0x05, bit 7, disables SMBus master mode. This prevents the DS100DF410 from trying to take command
of the SMBus to read from the external EEPROM. Obviously this bit will have no effect if the EEPROM read has
already taken place. It also has no effect if an EEPROM read is currently in progress. The only situations in
which disabling EEPROM master mode read is valid are (1) when the DS100DF410 is in SMBus master mode,
but the READ_EN pin has not yet gone low, and (2) when register 0x04, bit 5, has been used to reset SMBus
master mode but the EEPROM read operation has not yet occurred.
Do not set this bit and bit 4 of register 0x04 simultaneously. This is an undefined condition and can cause the
DS100DF410 to hang up.
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