DS100DF410 Datasheet, PDF (19/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
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Address (Hex)
Bits
0x00
7:4
0x01
7:5
4:0
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
Table 3. Control/Shared Registers
Default Value (Hex)
0x0
Mode
R
0x6
R
0x10
R
Description
SMBus Address Strap
Observation <3:0>
Device Revision
Device ID
0x04
6
5
4
0x05
7
4
3
2
1
0
0x06
3:0
0xff
3
2
0x0
R/W/SC
0x0
R/W
0x0
R/W
0x0
R/W
(1)
R
0x0
R
0x0
R
0x0
R
0x0
R
0X0
R/W
0x0
R/W
0x0
R/W
1:0
0x0
R/W
(1) There is no default value. This bit always indicates whether the EEPROM read is complete or not.
Self-Clearing Reset for
Control/Shared Registers
Reset for SMBus Master
Mode
Force EEPROM
Configuration
Disable Master Mode
EEPROM Configuration
EEPROM Read Complete
Set on Channel 0 Interrupt
Set on Channel 1 Interrupt
Set on Channel 2 Interrupt
Set on Channel 3 Interrupt
Diagnostic Test Control
Set to 0xa to read SMBus
strap values from register
0x00
Selects All Channels for
Register Write
See Table 4
Enables Register Write to
One or All Channels and
Register Read from One
Channel
See Table 4
Selects Target Channel
for Register Reads and
Writes
See Table 4
SMBus Strap Observation
Register 0x00, bits 7:4 and register 0x06, bits 3:0
In order to communicate with the DS100DF410 over the SMBus, it is necessary for the SMBus controller to know
the address of the DS100DF410 . The address strap observation bits in control/shared register 0x00 are primarily
useful as a test of SMBus operation. There is no way to get the DS100DF410 to tell you what its SMBus address
is unless you already know what it is.
In order to use the address strap observation bits of control/shared register 0x00, it is necessary first to set the
diagnostic test control bits of control/shared register 0x06. This four-bit field should be written with a value of 0xa.
When this value is written to bits 3:0 of control/shared register 0x06, then the value of the SMBus address straps
can be read in register 0x00, bits 7:4. The value read will be the same as the value present on the
ADDR3:ADDR0 lines when the DS100DF410 was powered up. For example, if a value of 0x1 is read from
control/shared register 0x00, bits 7:4, then at power-up the ADDR0 line was set to 1 and the other address lines,
ADDR3:ADDR1, were all set to 0. The DS100DF410 is set to an SMBus Write address of 0x32.
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