DS100DF410 Datasheet, PDF (28/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
www.ti.com
Overriding the VCO CAP DAC Values
Register 0x08, bits 4:0, Register 0x09, bit 7, Register 0x0b, bits 4:0, Register 0x36, bits 5:4, and Register 0x2f,
bits 7:6 and 5:4
Registers 0x08 and 0x0b contain CAP DAC override values. Normally, when bits 5:4 of register 0x36 are set to
2'b11, then the DS1010DF410 performs an initial search to determine the correct CAP DAC setting (coarse VCO
tuning) for the selected rate and subrate. The rate and subrate settings (bits 7:6 and 5:4 of register 0x2f)
determine the frequency range to be searched, with the 25 MHz reference clock used as the frequency reference
for the frequency search.
The CAP DAC value can be overridden by writing new values to bits 4:0 of register 0x08 (for CAP DAC setting 1)
and bits 4:0 of 0x0b (for CAP DAC setting 2). The override bit, bit 7 of register 0x09 must be set for the override
CAP DAC values to take effect. Since the valid rate and subrate setting for 10 GbE and 1 GbE applies to multiple
data rates, there are two CAP DAC values for this rate. The first is in register 0x08, bits 4:0, and the second is in
register 0x0b, bits 4:0. The DS100DF410 will use the CAP DAC value in register 0x08 for the larger divide ratio
(8) associated with the selected rate and subrate to try and acquire lock. If it fails to acquire lock, it will use the
CAP DAC value in register 0x0b with the smaller divide ratio (higher VCO frequency) associated with the
selected rate and subrate (1). It will continue to try to acquire lock in this way until it either succeeds or the
override bit (bit 7 of register 0x09) is cleared.
Overriding the Output Multiplexer
Register 0x09, bit 5, Register 0x14, bits 7:6, and Register 0x1e, bits 7:5
By default, the DS100DF410 output for each channel will be as shown in Table 6.
Input Signal Status
Not Present
Present
Present
Table 6. Default Output Status Description
Channel Status
No Signal Detected
Not Locked
Locked
Output Status
Muted
Muted
Retimed Data
This default behavior can be modified by register writes.
Register 0x1e, bits 7:5, contain the output multiplexer override value. The values of this three-bit field and the
corresponding meanings of each are shown in
Bit Field Value
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Table 7. Output Multiplexer Override Settings
Output Multiplexer Setting
Mute
N/A
10 MHz Clock
PRBS Generator
VCO Q-Clock
VCO I-Clock
Retimed Data
Raw Data
Comments
Default when no signal is present or when
the retimer is unlocked
Invalid Setting
Internal 10 MHz clock
Clock frequency may not be precise
PRBS Generator must be enabled to output
PRBS sequence
Register 0x09, bit 4, and register 0x1e, bit 0,
must be set to enable the VCO Q-Clock
Default when the retimer is locked
If the output multiplexer is not overridden, that is, if bit 5 of register 0x09 is not set, then the value in register
0x1e, bits 7:5, controls the output produced when the retimer has a signal at its input, but is not locked to it. The
default value for this bit field, 0x7, causes the retimer output to mute when the retimer is not locked to an input
signal. Writing a value of 0x0 to this bit field, for example, will cause the retimer to output raw data when it is not
locked to its input signal.
Setting the override bit, bit 5 of register 0x09, will cause the retimer to output the value selected by the bit field in
register 0x1e, bits 7:5, even when the retimer is locked.
28
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS100DF410