DS100DF410 Datasheet, PDF (32/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
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Under external SMBus control, the eye opening monitor can be programmed to sweep through all its 64 states of
phase and voltage offset autonomously. This mode is initiated by setting register 0x24, bit 7, the fast_eom mode
bit. Register 0x22, bit 7, the eom_ov bit, should be cleared in this mode.
When the fast_eom bit is set, the eye opening monitor operation is initiated by setting bit 0 of register 0x24,
which is self-clearing. As soon as this bit is set, the eye opening monitor begins to acquire eye data. The results
of the eye opening monitor error counter are stored in register 0x25 and 0x26. In this mode the eye opening
monitor results can be obtained by repeated multi-byte reads from register 0x25. It is not necessary to read from
register 0x26 for a multi-byte read. As soon as the eight most significant bits are read from register 0x25, the
eight least significant bits for the current setting are loaded into register 0x25 and they can be read immediately.
As soon as the read of the eight most significant bits has been initiated, the DS100DF410 sets its phase and
voltage offsets to the next setting and starts its error counter again. The result of this is that the data from the eye
opening monitor is available as quickly as it can be read over the SMBus with no further register writes required.
The external controller just reads the data from the DS100DF410 over the SMBus as fast as it can. When all the
data has been read, the DS100DF410 clears the eom_start bit.
If multi-byte reads are not used, meaning that the device is addressed each time a byte is read from it, then it is
necessary to read register 0x25 to get the MSB (the eight most significant bits) and register 0x26 to get the LSB
(the eight least significant bits) of the current eye monitor measurement. Again, as soon as the read of the MSB
has been initiated, the DS100DF410 sets its phase and voltage offsets to the next setting and starts its error
counter again. In this mode both registers 0x25 and 0x26 must be read in order to get the eye monitor data. The
eye monitor data for the next set of phase and voltage offsets will not be loaded into registers 0x25 and 0x26
until both registers have been read for the current set of phase and voltage offsets.
In all eye opening monitor modes, the amount of time during which the eye opening monitor accumulates eye
opening data can be set by the value of register 0x2a. In general, the greater this value the longer the
accumulation time. When this value is set to its maximum possible value of 0xff, the maximum number of
samples acquired at each phase and amplitude offset is approximately 2¹⁸. Even with this setting, the eye
opening monitor values can be read from the SMBus with no delay. The eye opening monitor operation is
sufficiently fast that the SMBus read operation cannot outrun it.
The eye opening is measured at the input to the data comparator. At this point in the data path, a significant
amount of gain has been applied to the signal by the CTLE. In many cases, the vertical eye opening as
measured by the EOM will be on the order of 400 to 500 mV peak-to-peak. The secondary comparator, which is
used to measure the eye opening, has an adjustable voltage range from ±100 mV to ±400 mV. The EOM voltage
range is normally set by the CDR state machine during lock and adaptation, but the range can be overridden by
writing a two-bit code to bits 7:6 of register 0x11. The values of this code and the corresponding EOM voltage
ranges are shown in Table 9.
Table 9. EOM Voltage Range vs. Bits 7:6 of Register 0x11
Value in Bits 7:6 of Register 0x11
0x0
0x1
0x2
0x3
EOM Voltage Range (± mV)
±100
±200
±300
±400
Note that the voltage ranges shown in Table 9 are the voltage ranges of the signal at the input to the data path
comparator. These values are not directly equivalent to any observable voltage measurements at the input to the
DS100DF410 . Note also that if the EOM voltage range is set too small the voltage sweep of the secondary
comparator may not be sufficient to capture the vertical eye opening. When this happens the eye boundaries will
be outside the vertical voltage range of the eye measurement.
Overriding the DFE Tap Weights and Polarities
Register 0x11, bits 3:0, Register 0x12, bit 7 and bits 4:0, Register 0x15, bit 7, Register 0x1e, bit 3, Register 0x20,
Register 0x21, Register 0x23, bit 6, Register 0x24, bit 2, Register 0x2f, bit 0, and Registers 0x71–0x75
For the DS100DF410 the DFE tap weights and polarities are normally set automatically by the adaptation
procedure. These values can be overridden by the user if desired.
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