DS100DF410 Datasheet, PDF (33/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
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SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
Prior to overriding the DFE tap weights and polarities, the dfe_ov bit, bit 6 of register 0x23, should be set. This bit
is set by default. In order for the DFE tap weights and polarities to be applied to the input signal, bit 3 of register
0x1e, the dfe_PD bit, must be set to 0. It is necessary to change the default settings of these registers, because
the DFE is powered down by default.
It is also necessary to set bit 7 of register 0x15 in order to manually set the DFE tap weights. This bit is cleared
by default.
Bits 4:0 of register 0x12 set the five-bit weight for DFE tap 1. The first DFE tap has a five-bit setting, while the
other taps are set using four bits. Often the first DFE tap has the largest effect in improving the bit error rate of
the system, which is why this tap has a five-bit weight setting.
The polarity of the tap weight for tap 1 is set using bit 7 of the same register, register 0x12. The polarity is set to
0 by default, which corresponds to a negative algebraic sign for the tap.
The other four taps are set using four-bit fields in registers 0x20 and 0x21. The polarities of these taps are set by
bits 3:0 in register 0x11. These tap polarities are all set to 0 by default.
As is the case for the CTLE settings, if changing the DFE tap weights or polarities causes the DS100DF410 to
lose lock, it may readapt its CTLE in order to reacquire lock. If this occurs, the CTLE settings may appear to
change spontaneously when the DFE tap weights are changed. The mechanism is the same as that described
above for the CTLE boost settings.
When the DS100DF410 is set to adapt mode 2 or 3 using bits 6:5 of register 0x31, it will automatically adapt its
DFE whenever its CDR state machine is reset. This occurs when the user manually resets the CDR state
machine using bits 3:2 of register 0x0a, or when a signal is first presented at the input to the channel when the
channel is in an unlocked state.
Regardless of the adapt mode, DFE adaptation can be initiated under SMBus control. Because the DFE tap
weight registers are used by the DFE state machine during adaptation, they may be reset prior to adaptation,
which can cause the adaptation to fail. The DFE tap observation registers can be used to prevent this.
Prior to initiating DFE adaptation under SMBus control, write the starting values of the DFE tap settings into the
DFE tap weight registers, registers 0x11, 0x12, 0x20, and 0x21. The values can be read from the observation
registers, registers 0x71 through 0x75. For each DFE tap, read the current value in the observation register. Both
the polarities and the tap weights are contained in the observation registers as shown in Table 3. For each DFE
tap, write the current tap polarity and tap weight into the DFE tap register. Once all these values have been
written, DFE adaptation can be initiated and it will proceed normally. If the DS100DF410 fails to find a set of DFE
tap weights producing a better adaptation figure of merit than the starting tap weights, the starting tap weights
will be retained and used.
CTLE adaptation can also be initiated manually. Setting and then clearing bit 0 of register 0x2f will initiate
adaptation of the CTLE. As with the DFE, if the DS100DF410 fails to find a set of CTLE settings that produce a
better adaptation figure of merit than the starting CTLE values, the starting CTLE values will be retained and
used.
Enabling Slow Rise/Fall Time on the Output Driver
Register 0x18, bit 2
Normally the rise and fall times of the output driver of the DS100DF410 are set by the slew rate of the output
transistors. By default, the output transistors are biased to provide the maximum possible slew rate, and hence
the minimum possible rise and fall times. In some applications, slower rise and fall times may be desired. For
example, slower rise and fall times may reduce the amplitude of electromagnetic interference (EMI) produced by
a system.
Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal.
Setting this bit will approximately double the nominal rise and fall times of the DS100DF410 output driver. This bit
is cleared by default.
Inverting the Output Polarity
Register 0x1f, bit 7
In some systems, the polarity of the data does not matter. In systems where it does matter, it is sometimes
necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals.
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