DS100DF410 Datasheet, PDF (22/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
www.ti.com
Address (Hex)
Bits
0x00
2
0x01
4
0
0x03
7:6
5:4
3:2
1:0
0x08
4:0
0x09
7
5
2
0x0a
3
2
0x0b
4:0
0x0d
5
0x11
7:6
5
3
2
1
0
0x12
7
4:0
0x13
2
0x14
7
6
0x15
7
6
Table 5. Channel Registers
Default Value (Hex) Mode
0x0
R/W/SC
0x0
R
0x0
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x00
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0f
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x00
R/W
0x0
RW
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Field Name
Description
rst_regs
Reset Channel
Registers to Defaults
(Self-clearing)
cdr_lock_loss_int
CDR Lock Loss
Interrupt
signal_detect_loss_int Signal Detect Loss
Interrupt
eq_BST0[1:0]
CTLE Boost Stage 0
<1:0>
eq_BST1[1:0]
CTLE Boost Stage 1
<1:0>
eq_BST2[1:0]
CTLE Boost Stage 2
<1:0>
eq_BST3[1:0]
CTLE Boost Stage 3
<1:0>
cdr_cap_dac_start[4: Override Starting
0]
VCO Cap DAC
Setting 0 <4:0>
reg_divsel_vco_cap_ Enable Override VCO
ov
Cap DAC (Registers
0x08 and 0x0b)
reg_bypass_pfd_ov
Enable Override
Output Mux (Register
0x1e)
reg_divsel_ov
Enable Override
Divider Select
(Register 0x18)
reg_cdr_reset_ov
Enable CDR Reset
Override (Register
0x0a)
reg_cdr_reset_sm
CDR Reset Override
Bit
cdr_cap_dac_start1[4 Override VCO Cap
:0]
DAC Setting 1 <4:0>
PRBS_PATT_SHIFT_ PRBS Generator
EN
Clock Enable
eom_sel_vrange[1:0] Eye Opening Monitor
Voltage Range <1:0>
eom_PD
Eye Opening Monitor
Power Down
dfe_tap2_pol
DFE Tap 2 Polarity
dfe_tap3_pol
DFE Tap 3 Polarity
dfe_tap4_pol
DFE Tap 4 Polarity
dfe_tap5_pol
DFE Tap 5 Polarity
dfe_tap1_pol
DFE Tap 1 Polarity
dfe_wt1[4:0]
DFE Tap 1 Weight
<4:0>
eq_BST3[2]
CTLE Boost Stage 3,
Bit 2 (Limiting Bit)
eq_sd_preset
Force Signal Detect
On
eq_sd_reset
Force Signal Detect
Off
dfe_manual_tap_en Enables manual DFE
tap settings
drv_dem_range
Driver De-emphasis
Range
22
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