DS100DF410 Datasheet, PDF (13/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
www.ti.com
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
Driver Output De-Emphasis
The output de-emphasis level of the DS100DF410 can be configured from a nominal setting of 0 dB to a nominal
setting of -12 dB depending upon the application. Larger absolute values of the de-emphasis setting provide
more pre-distortion of the output driver waveform, accentuating the high-frequency components of the output
driver waveform relative to the low-frequency components. Greater values of de-emphasis can compensate for
greater dispersion in the transmission media at the output of the DS100DF410. The output de-emphasis level as
set is the typical value to which the output signal will settle following the de-emphasis pulse interval in dB relative
to the output VOD.
Driver Output Rise/Fall Time
In some applications, a longer rise/fall time for the output signal is desired. This can reduce electromagnetic
interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory
compliance. In others, it can reduce the crosstalk in the system.
The DS100DF410 can be configured to operate with a nominal rise/fall time corresponding to the maximum slew
rate of the output drivers into the load capacitance. Alternatively, the DS100DF410 can be configured to operate
with a slightly greater rise/fall time if desired. For the typical specifications on rise/fall time, see Electrical
Characteristics
Ref_mode 0 Mode (reference clock not required)
The DS100DF410 can be used without using a reference clock and the input REFCLK_IN pin can be open.
When register 0x36, bits [5:4] are set to 2’b00, the device operates without using a reference clock at 10.3125
Gbps mode.
For 1GbE applications, it is required to bypass the CDR by setting the override bit 5 of register 0x09 to 1, and set
the data mux bits [7:5] to 3'b000 of register 0x1E.
Ref_mode 3 Mode (reference clock required)
When using ref_mode 3, the device uses an external 25 MHz clock. This mode of operation is set in register
0x36 bits [5:4] = 2'b11 and is the default setting. In ref_mode 3, the external reference clock is used to aid initial
phase lock, and to determine when its VCO is properly phase-locked. An external oscillator should be used to
generate a 2.5V, 25 MHz reference signal which is connected to the DS100DF410 on the reference clock input
pin (pin 19). The DS100DF410 does not include a crystal oscillator circuit, so a stand-alone external oscillator is
required.
The reference clock speeds up the initial phase lock acquisition. The DS100DF410 is set to phase lock to a
known data rate, or a constrained set of known data rates, and the digital circuitry in the DS100DF410 pre-
configures the VCO frequency. This enables the DS100DF410 phase-lock to the incoming signal very quickly.
The reference clock is used to calibrate the VCO coarse tuning. However, the reference clock is not synchronous
to the data stream, and the quality of the reference clock does not affect the jitter on the output retimed data. The
retimed data clock for each channel is synchronous to the VCO internal to that channel of the DS100DF410.
The phase noise of the reference clock is not critical. Any commercially-available 25 MHz oscillator can provide
an acceptable reference clock. The reference clock can be daisy-chained from one retimer to another so that
only one reference oscillator is required in a system.
False Lock Detector Setting
The register 0x2F, bit 1 is set to 1 by default, which disables the false lock detector. This bit must be set to 0 to
enable the false lock detector function.
Reference Clock In
REFCLK_IN pin 19 is for reference clock input. A 25 MHz oscillator should be connected to pin 19. See Electrical
Characteristics for the requirements on the 25 MHz clock. The frequency of the reference clock should always be
25 MHz no matter what data rate or mode of operation is used.
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