DS100DF410 Datasheet, PDF (31/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
www.ti.com
SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
The VCO frequency in free-run will vary somewhat from part to part. In order to determine exact values of the
CAP DAC and LPF DAC settings, it will be necessary to directly measure the VCO frequency using some sort of
frequency-measurement device such as a frequency counter or a spectrum analyzer. When the VCO is set to
free-run mode as above, you can select the VCO I-clock (in-phase clock) to be the output as shown in Table 7.
You can measure the frequency of the VCO I-clock while adjusting the CAP DAC and LPF DAC values until the
VCO I-clock frequency is acceptable for your application. Then you can once again select the PRBS generator
as the output using the output multiplexer selection field.
Using the Internal Eye Opening Monitor
Register 0x11, bits 7:6 and bit 5, Register 0x22, bit 7, Register 0x24, bit 7 and bit 0, Register 0x25, Register
0x26, Register 0x27, Register 0x28, and Register 0x2a
The DS100DF410 includes an internal eye opening monitor. The eye opening monitor is used by the retimer to
compute a figure of merit for automatic adaptation of the CTLE and the DFE. It can also be controlled and
queried through the SMBus by a system controller.
The eye opening monitor produces error hit counts for settable phase and voltage offsets of the comparator in
the retimer. This is similar to the way many Bit Error Rate Test Sets measure eye opening. At each phase and
amplitude offset setting, the eye opening monitor determines the nominal bit value (“0” or “1”) using its primary
comparator. This is the bit value that is resynchronized to the recovered clock and presented at the output of the
DS100DF410. The eye opening monitor also determines the bit value detected by the offset comparator. This
information yields an eye contour. Here's how this works.
If the offset comparator is offset in voltage by an amount larger than the vertical eye opening, for example, then
the offset comparator will always decide that the current bit has a bit value of “0”. When the bit is really a “1”, as
determined by the primary comparator, this is considered a bit error. The number of bit errors is counted for a
settable interval at each setting of the offset phase and voltage of the offset comparator. These error counts can
be read from registers 0x25 and 0x26 for sequential phase and voltage offsets. These error counts for each
phase and voltage offsets form a 64 X 64 point array. A surface or contour plot of the error hit count versus
phase and voltage offset produces an eye diagram, which can be plotted by external software.
The eye opening monitor works in two modes. In the first, only the horizontal and vertical eye openings are
measured. The eye opening monitor first sweeps its variable-phase clock through one unit interval with the
comparison voltage set to the mid point of the signal. This determines the midpoint of the horizontal eye opening.
The eye opening monitor then sets its variable phase clock to the midpoint of the horizontal eye opening and
sweeps its comparison voltage. These two measurements determine the horizontal and vertical eye openings.
The horizontal eye opening value is read from register 0x27 and the vertical eye opening from register 0x28.
Both values are single byte values.
The measurement of horizontal and vertical eye opening is very fast. The speed of this measurement makes it
useful for determining the adaptation figure of merit. In normal operation, the HEO and VEO are automatically
measured periodically to determine whether the DS100DF410 is still in lock. Reading registers 0x27 and 0x28
will yield the most-recently measured HEO and VEO values.
In normal operation, the eye monitor circuitry is powered down most of the time to save power. When the eye is
to be measured under external control, it must first be enabled by writing a 0 to bit 5 of register 0x11. The default
value of this bit is 1, which powers down the eye monitor except when it is powered-up periodically by the CDR
state machine and used to test CDR lock. The eye monitor must be powered up to measure the eye under
external SMBus control.
Bits 7:6 of register 0x11 are also used during eye monitor operation to set the EOM voltage range. This is
described below. A single write to register 0x11 can set both bit 5 and bits 7:6 in one operation.
Register 0x3e, bit 7, enables horizontal and vertical eye opening measurements as part of the lock validation
sequence. When this bit is set, the CDR state machine periodically uses the eye monitor circuitry to measure the
horizontal and vertical eye opening. If the eye openings are too small, according to the pre-determined
thresholds in register 0x6a, then the CDR state machine declares lock loss and begins the lock acquisition
process again. For SMBus acquisition of the internal eye, this lock monitoring function must be disabled. Prior to
overriding the EOM by writing a 1 to bit 0 of register 0x24, disable the lock monitoring function by writing a 0 to
bit 7 of register 0x3e. Once the eye has been acquired, you can reinstate HEO and VEO lock monitoring by once
again writing a 1 to bit 7 of register 0x3e.
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