DS100DF410 Datasheet, PDF (27/43 Pages) Texas Instruments – Low Power 10GbE Quad Channel Retimer

DS100DF410
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SNLS399A – JANUARY 2012 – REVISED FEBRUARY 2013
register is set, then the interrupt was caused by a loss of CDR lock. If bit 0 is set, then the interrupt was
caused by a loss of signal. it is possible that both bits 0 and 4 could be set. Reading this register will clear
these bits.
6. Optionally, for each channel that generated an interrupt, the controller reads channel register 0x30. If bit 4 of
this register is set, then the interrupt was caused by HEO and/or VEO falling out of the configured range.
This interrupt will only occur if bit 6 of channel register 0x36 is set, enabling the HEO/VEO interrupt. Reading
register 0x30 will clear this interrupt bit.
7. Once the controller has determined what condition caused the interrupt, the controller can then take the
appropriate action. For example, the controller might reset the CDR to cause the retimer to re-adapt to the
incoming signal. If there is no longer an incoming signal (indicated by a loss of signal interrupt, bit 0 of
channel register 0x01), then the controller might alert an operator or change the channel configuration. This
is system dependent.
8. Reading the interrupt status registers will clear the interrupt. if this does not cause the interrupt input to go
high, then another device on the same input has generated an interrupt. The controller can address the next
device using the procedure above.
9. Once all the interrupt registers for all channels for all DS100DF410s that generated interrupts have been
read, clearing all the interrupt indications, the INT line should go high again. This indicates that all the
existing interrupt conditions have been serviced.
The channel registers referred to above, registers 0x01, 0x30, 0x32, and 0x36, are described in the channel
registers table, Table 5.
Overriding the CTLE Boost Setting
Register 0x03, Register 0x13, bit 2, and Register 0x3a
To override the CTLE boost settings, register 0x03 is used. This register contains the currently-applied CTLE
boost settings. The boost values can be overridden by using the two-bit fields in this register as shown in the
table.
The final stage of the CTLE has an additional control bit which sets it to a limiting mode. For some channels, this
additional setting improves the bit error rate performance. This bit is bit 2 of register 0x13.
If the DS100DF410 loses lock because of a change in the CTLE settings, the DS100DF410 will initiate its lock
and adaptation sequence again. Thus, if you write new CTLE boost values to register 0x03 and 0x13 which
cause the DS100DF410 to drop out of lock, the DS100DF410 may, in the process of reacquiring the CDR lock,
reset the CTLE settings to different values than those you set in register 0x03 and 0x13. If this behavior is not
understood, it can appear that the DS100DF410 did not accept the values you wrote to the CTLE boost registers.
What's really happening, however, is that the lock and adaptation sequence is overriding the CTLE values you
wrote to the CTLE boost registers. This will not happen unless the DS100DF410 drops out of lock.
if the adapt mode is set to 0 (bits 6:5 of channel register 0x31), then the CTLE boost values will not be
overridden, but the DS100DF410 may still lose lock. If this happens, the DS100DF410 will attempt to reacquire
lock. if the reference mode is set correctly, and if the rate/subrate code is set to permit it, the DS100DF410 will
begin searching for CDR lock at the highest allowable VCO divider ratio – that is, at the lowest configured bit
rate. At this lowest bit rate, the CTLE boost settings used will come not from the values in register 0x03, and
0x13, but rather from register 0x3a, the fixed CTLE boost setting for lower data rates. This setting will be written
into boost setting register 0x03 during the lock search process. This value may be different from the value you
set in register 0x03, so, again, it may appear that the DS100DF410 has not accepted the CTLE boost settings
you set in registers 0x03 and 0x13. The interactions of the lock and adaptation sequences with the manually-set
CTLE boost settings can be difficult to understand.
To manually override the CTLE boost under all conditions, perform the following steps.
1. Set the DS100DF410 channel adapt mode to 0 by writing 0x0 to bits 6:5 of channel register 0x31.
2. Set the desired CTLE boost setting in register 0x3a. If the DS100DF410 loses lock and attempts to lock to a
lower data rate, it will use this CTLE boost setting.
3. Set the desired CTLE boost setting in register 0x03. This may cause the DS100DF410 to lose lock.
4. If desired, set the CTLE stage 3 limiting bit, bit 2 of register 0x13.
If the DS100DF410 loses lock when the CTLE boost settings are set according to the sequence above, the
DS100DF410 will try to reacquire lock, but it will not change the CTLE boost settings in order to do so.
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