SM59R02G1 Datasheet, PDF (53/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
memory program/erase timing so the locked ISP service program can not be erased by flash erase function. If user
needs to erase the locked ISP service program, he can do it by writer only. User can not change ISP service program
when SM59R02G1 was in system.
13.4. Initiate ISP Service Program
To initiate the ISP service program is to load the program counter (PC) with start address of ISP service program and
execute it. There are four ways to do so:
(1) Blank reset. Hardware reset with first flash address blank ($0000=#FFH) will load the PC with start
address of ISP service program. The hardware reset includes Internal (power on reset) and external
pad reset.
(2) Execute jump instruction can load the start address of the ISP service program to PC.
(3) Enters ISP service program by hardware setting. User can force SM59R02G1 enter ISP service
program by setting P2.6, P2.7 “active low” or P4.3 “ active low” during hardware reset period. The
hardware reset includes Internal (power on reset) and external pad reset. In application system
design, user should take care of the setting of P2.6, P2.7 or P4.3 at reset period to prevent
SM59R02G1 from entering ISP service program.
(4) Enter’s ISP service program by hardware setting, the port3.0 will be detected the two clock signals
during hardware reset period. The hardware reset includes Internal (power on reset) and external
pad reset. And detect 2 clock signals after hardware reset.
During hardware reset period, the hardware will detect the status of P2.6/P2.7/P4.3/P3.0. If they meet one of above
conditions, chip will switch to ISP mode automatically. After ISP service program executed, user need to reset the
SM59R02G1, either by hardware reset or by WDT, or jump to the address $0000 to re-start the firmware program.
There are 8 kinds of entry mechanisms for user different applications. This entry method will select on the writer or
ISP.
(1) First Address Blank. i.e. $0000 = 0xFF. And triggered by Internal reset signal.
(2) First Address Blank. i.e. $0000 = 0xFF. And triggered by PAD reset signal.
(3) P2.6 = 0 & P2.7 = 0. And triggered by Internal reset signal.
(4) P2.6 = 0 & P2.7 = 0. And triggered by PAD reset signal.
(5) P4.3 = 0. And triggered by Internal reset signal.
(6) P4.3 = 0. And triggered by PAD reset signal.
(7) P3.0 input 2 clocks. And triggered by Internal reset signal.
(8) P3.0 input 2 clocks. And triggered by PAD reset signal.
13.5. ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC
Mnemonic
TAKEY
IFCON
ISPFAH
ISPFAL
ISPFD
ISPFC
Description
Time Access Key
register
Interface Control
register
ISP Flash
Address - High
register
ISP Flash
Address - Low
register
ISP Flash Data
register
ISP Flash Control
register
Direct
F7h
8Fh
E1h
E2h
E3h
E4h
Bit 7
ITS
-
EMF1
Bit 6 Bit 5
ISP function
CDPR
-
-
-
EMF2 EMF3
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TAKEY [7:0]
-
ALEC[1:0]
-
ISPE
ISPFAH [4:0]
ISPFAL [7:0]
ISPFD [7:0]
EMF4
-
ISPF.2 ISPF.1 ISPF.0
RESET
00H
00H
FFH
FFH
FFH
00H
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
53
Ver.G SM59R02G1 09/2015