SM59R02G1 Datasheet, PDF (31/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
11
Mode3
If Timer 1 M1 and M0 bits are set to 1, Timer 1
stops. If Timer 0 M1 and M0 bits are set to 1,
Timer 0 acts as two independent 8 bit timers /
counters.
6.2. Timer/counter control register (TCON)
Mnemonic: TCON
7
6
5
4
3
TF1 TR1 TF0 TR0
IE1
Address: 88h
2
1
0 Reset
IT1
IE0
IT0 00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1
is observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT0
is observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
6.3. Peripheral Frequency control register(PFCON)
Mnemonic: PFCON
7
6
5
4
-
-
S0RELPS[1:0]
3
2
T1PS[1:0]
Address: D9h
1
0 Reset
T0PS[1:0]
00H
T1PS[1:0]: Timer1 Prescaler select
T1PS[1:0]
Prescaler
00
Fosc/12
01
Fosc
10
Fosc/96
11
reserved
T0PS[1:0]: Timer0 Prescaler select
T0PS[1:0]
Prescaler
00
Fosc/12
01
Fosc
10
Fosc/96
11
reserved
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
31
Ver.G SM59R02G1 09/2015