SM59R02G1 Datasheet, PDF (44/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
becoming active.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The WDTF flag can be
clear by software or external reset or power on reset.
250KHz RC
oscillator
Clear
1. Power on reset WDTF = 0
2. External reset
3. Software write “0”
WDTF
Set WDTF = 1
TAKEY
(55, AA, 5A)
1
2^WDTM
WDTM[3:0]
WDTC
Enable WDTC
write attribute
WDTEN
WDTCLK
Enable/Disable
WDT
WDT
Counter
Refresh
WDT Counter
WDT
time-out
select
CWDTR = 0
WDT time-out
reset
WDT time-out
CWDTR = 1 Interrupt
WDTK
(0x55)
Fig. 9-1: Watchdog timer block diagram
Mnemonic Description
Direct
TAKEY
Time Access Key
register
F7h
WDTC
Watchdog timer
control register
B6h
WDTK
Watchdog timer
refresh key
B7h
RSTS
Reset Status Flag
register
A1h
Bit 7
-
-
Bit 6
Bit 5 Bit 4
Watchdog Timer
Bit 3
TAKEY [7:0]
Bit 2
Bit 1
Bit 0
CWDTR WDTE -
WDTM [3:0]
WDTK[7:0]
-
-
PDRF WDTF SWRF LVRF PORF
RESET
00H
04H
00H
00H
Mnemonic: TAKEY
7
6
5
4
3
2
TAKEY [7:0]
Address: F7h
1
0
Reset
00H
Watchdog timer control register (WDTC) is read-only by default; software must write three specific
values 55h, AAh and 5Ah sequentially to the TAKEY register to enable the WDTC write attribute. That is:
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
Mnemonic: WDTC
7
6
5
4
-
CWDTR WDTE
-
Address: B6h
3
2
1
0
Reset
WDTM [3:0]
04H
CWDTR: 0: watchdog reset
1: watchdog interrupt
WDTE: Control bit used to enable Watchdog timer.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
44
Ver.G SM59R02G1 09/2015