SM59R02G1 Datasheet, PDF (45/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
The WDTE bit can be used only if WDTEN is "0". If the WDTEN bit is "0", then WDT
can be disabled / enabled by the WDTE bit.
0: Disable WDT.
1: Enable WDT.
The WDTE bit is not used if WDTEN is "1". That is, if the WDTEN bit is "1", WDT is
always disabled no matter what the WDTE bit status is. The WDTE bit can be read and
written.
WDTM [3:0]: WDT clock source divider bit. Please see table 7.8.1 to reference the WDT time-out
period.
Mnemonic: WDTK
Address: B7h
7
6
5
4
3
2
1
0 Reset
WDTK[7:0]
00h
WDTK: Watchdog timer refresh key.
A programmer must write 0x55 into WDTK register, and then the watchdog
timer will be cleared to zero.
For example, if enable WDT and select time-out reset period is 327.68ms.
First, programming the information block OP3 bit7 WDTEN to “0”.
Secondly,
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah
; enable WDTC write attribute.
MOV WDTC, #28h
; Set WDTM [3:0] = 1000b. Set WDTE =1 to enable WDT
; function.
.
.
MOV WDTK, #55h
; Clear WDT timer to 0.
Mnemonic: RSTS
Address: B6h
7
6
5
4
3
2
1
0
Reset
-
-
-
PDRF WDTF SWRF LVRF PORF 00H
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware.
This flag clear by software or external reset or power on reset.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
45
Ver.G SM59R02G1 09/2015