SM59R02G1 Datasheet, PDF (27/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
4.6. Data Pointer 1
The Dual Data Pointer accelerates the moves of data block. The standard DPTR is a 16-bit register that is used to
address external memory or peripherals. In the SM59R02G1 core the standard data pointer is called DPTR, the second
data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located
in LSB of AUX register (DPS).
The user switches between pointers by toggling the LSB of AUX register. All DPTR-related instructions use the currently
selected DPTR for any activity.
Mnemonic: DPL1
7
6
5
4
3
DPL1 [7:0]
Address: 84h
2
1
0 Reset
00h
DPL1[7:0]: Data pointer Low 1
Mnemonic: DPH1
7
6
5
4
3
DPH1 [7:0]
Address: 85h
2
1
0 Reset
00h
DPH1[7:0]: Data pointer High 1
Mnemonic: AUX
7
6
5
4
3
BRGS
-
-
P1UR
-
Address: 91h
2
1
0 Reset
-
-
DPS 00H
DPS: Data Pointer selects register.
DPS = 1 is selected DPTR1.
4.7. Interface control register
Mnemonic: IFCON
7
6
5
4
ITS CDPR
-
-
3
2
ALEC[1:0]
Address: 8Fh
1
0 Reset
-
ISPE 00h
ITS: Instruction timing select. (default is 2T)
ITS = 0, 2T instruction mode.
ITS = 1, 1T instruction mode.
CDPR: code protect (Read Only)
ALEC[1:0]: ALE output control register.
ALEC[1:0] ALE Output
00
Always output
01
No ALE output
10
Only Read or Write have ALE output
11
reserved
ISPE: ISP function enable bit
ISPE = 1, enable ISP function
ISPE = 0, disable ISP function
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
27
Ver.G SM59R02G1 09/2015