SM59R02G1 Datasheet, PDF (25/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
4. CPU Engine
The SM59R02G1 engine is composed of four components:
a. Control unit
b. Arithmetic – logic unit
c. Memory control unit
d. RAM and SFR control unit
The SM59R02G1 engine allows to fetch instruction from program memory and to execute using RAM or SFR. The
following paragraphs describe the main engine registers.
Mnemonic
ACC
B
PSW
SP
DPL
DPH
DPL1
DPH1
AUX
IFCON
Description
Accumulator
B register
Program status
word
Stack Pointer
Data pointer low 0
Data pointer high
0
Data pointer low 1
Data pointer high
1
Auxiliary register
Interface control
register
Direct
E0h
F0h
D0h
81h
82h
83h
84h
85h
91h
8Fh
Bit 7
ACC.7
B.7
Bit 6 Bit 5
8051 Core
ACC.6 ACC.5
B.6
B.5
Bit 4
ACC.4
B.4
Bit 3
ACC.3
B.3
Bit 2
ACC.2
B.2
Bit 1
ACC.1
B.1
Bit 0
ACC.0
B.0
CY
AC
F0
RS[1:0]
OV PSW.1 P
SP[7:0]
DPL[7:0]
DPH[7:0]
DPL1[7:0]
DPH1[7:0]
BRGS
-
-
P1UR
-
-
-
DPS
ITS CDPR
-
-
ALEC[1:0]
-
ISPE
RESET
00H
00H
00H
07H
00H
00H
00H
00H
00H
00H
4.1. Accumulator
ACC is the Accumulator register. Most instructions use the accumulator to store the operand.
Mnemonic: ACC
7
6
5
ACC.7 ACC.6 ACC05
4
ACC.4
3
ACC.3
2
ACC.2
1
ACC.1
Address: E0h
0
Reset
ACC.0 00h
ACC[7:0]: The A (or ACC) register is the standard 8052 accumulator.
4.2. B Register
The B register is used during multiply and divide instructions. It can also be used as a scratch pad register to store
temporary data.
Mnemonic: B
Address: F0h
7
6
5
4
3
2
1
0
Reset
B.7
B.6
B.5
B.4
B.3
B.2
B.1
B.0
00h
B[7:0]: The B register is the standard 8052 register that serves as a second accumulator.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
25
Ver.G SM59R02G1 09/2015