SM59R02G1 Datasheet, PDF (18/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
1.4.5. Reset Status Flag(RSTS)
Mnemonic: RSTS
7
6
5
-
-
-
4
PDRF
3
2
WDTF SWRF
1
LVRF
Address: A1H
0
Reset
PORF 00H
PDRF: Pad reset flag.
When MCU is reset by reset pad, PDRF flag will be set to one by hardware. This flag clear by
software.
WDTF: Watchdog timer reset flag.
When MCU is reset by watchdog, WDTF flag will be set to one by hardware. This flag clear by
software.
SWRF: Software reset flag.
When MCU is reset by software, SWRF flag will be set to one by hardware. This flag clear by
software.
LVRF: Low voltage reset flag.
When MCU is reset by LVR, LVRF flag will be set to one by hardware. This flag clear by software.
PORF: Power on reset flag.
When MCU is reset by POR, PORF flag will be set to one by hardware. This flag clear by
software.
1.4.6. Example of software reset
MOV TAKEY, #55h
MOV TAKEY, #AAh
MOV TAKEY, #5Ah ; enable SWRES write attribute
MOV SWRES, #FFh ; software reset MCU
1.5. Clocks
The default clock is the 22.1184MHz Internal OSC. This clock is used during the initialization stage. The major work of the
initialization stage is to determine the clock source used in normal operation.
The internal clock sources are from the internal OSC with difference frequency division as given in table 1-1, the clock
source can set by writer。
Table 1-1: Selection of clock source
Clock source
external crystal
External OSC into Xtal1
22.1184 MHz from internal OSC(default)
11.0592MHz from internal OSC
5.5296MHz from internal OSC
2.7648MHz from internal OSC
1.3824MHz from internal OSC
The internal OSC have ±2％ variance at room temperature.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
18
Ver.G SM59R02G1 09/2015