SM59R02G1 Datasheet, PDF (48/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
Interrupt request register 2(IRCON2)
Mnemonic: IRCON2
Address: 97h
7
6
5
4
3
2
1
0
Reset
-
-
-
-
-
-
WDTIF
-
00H
WDTIF: WDT interrupt flag.
Priority level structure
All interrupt sources are combined in groups:
Table 10-2: Priority level groups
Groups
External interrupt 0
-
Timer 0 interrupt
-
External interrupt 1
WDT interrupt
Timer 1 interrupt
-
Serial channel 0 interrupt
-
Timer 2 interrupt
-
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit
in the special function register IP0 and one in IP1. If requests of the same priority level will be received simultaneously, an
internal polling sequence determines which request is serviced first.
Mnemonic: IP0
7
6
-
-
5
IP0.5
4
IP0.4
3
IP0.3
2
IP0.2
1
IP0.1
Address: A9h
0 Reset
IP0.0 00h
Mnemonic: IP1
7
6
-
-
5
IP1.5
4
IP1.4
3
IP1.3
2
IP1.2
1
IP1.1
Address: B9h
0 Reset
IP1.0 00h
Table 10-3: Priority levels
IP1.x IP0.x
Priority Level
0
0
Level0 (lowest)
0
1
Level1
1
0
Level2
1
1
Level3 (highest)
Bit
IP1.0, IP0.0
IP1.1, IP0.1
IP1.2, IP0.2
IP1.3, IP0.3
IP1.4, IP0.4
IP1.5, IP0.5
Table 10-4: Groups of priority
Group
External interrupt 0
Timer 0 interrupt
External interrupt 1
Timer 1 interrupt
Serial channel 0 interrupt
Timer 2 interrupt
-
WDT interrupt
-
-
-
-
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
48
Ver.G SM59R02G1 09/2015