SM59R02G1 Datasheet, PDF (39/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
8. Serial interface 0
As the conventional UART, the communication speed can be selected by configuring the baud rate in SFRs.
These two serial buffers consists of two separate registers, a transmit buffer and a receive buffer. Writing data to the
SFR S0BUF sets this data in serial output buffer and starts the transmission. Reading from the S0BUF reads data from
the serial receive buffer. The serial port can simultaneously transmit and receive data. It can also buffer 1 byte at
receive, which prevents the receive data from being lost if the CPU reads the second byte before the transmission of the
first byte is completed.
Mnemonic Description
PCON
AUX
S0CON
S0RELL
S0RELH
S0BUF
PFCON
Power control
Auxiliary
register
Serial Port 0
control register
Serial Port 0
reload register
low byte
Serial Port 0
reload register
high byte
Serial Port 0
data buffer
Peripheral
Frequency
control register
Direct
87h
91h
Bit 7
SMOD
BRGS
Bit 6 Bit 5 Bit 4
Serial interface 0
-
-
-
-
-
P1UR
Bit 3
-
-
Bit 2
-
-
Bit 1
STOP
-
Bit 0
IDLE
DPS
RESET
40h
00H
98h
SM0 SM1 SM20 REN0 TB80 RB80 TI0
RI0
00h
AAh
S0REL S0REL S0REL S0REL S0REL S0REL S0REL S0REL
.7
.6
.5
.4
.3
.2
.1
.0
00h
BAh
-
-
-
-
-
-
S0REL S0REL
.9
.8
00h
99h
S0BUF[7:0]
00h
D9H
S0RELPS[1:0]
T1PS[1:0]
T0PS[1:0]
00H
Mnemonic: AUX
7
6
5
4
3
2
BRGS
-
-
P1UR
-
-
Address: 91h
1
0 Reset
-
DPS 00H
BRGS: Baud rate generator.
BRGS = 0 - baud rate generator from Timer 1.
BRGS = 1 - baud rate generator by S0REL.
P1UR: P1UR = 0 – Serial interface function on P3.
P1UR = 1 – Serial interface function on P1.
Mnemonic: S0CON
7
6
5
4
3
2
1
SM0 SM1 SM20 REN0 TB80 RB80 TI0
Address: 98h
0 Reset
RI0 00h
SM0,SM1: Serial Port 0 mode selection.
SM0 SM1 Mode
0
0
0
0
1
1
1
0
2
1
1
3
The 4 modes in UART0, Mode 0 ~ 3, are explained later.
SM20: Enables multiprocessor communication feature
REN0: If set, enables serial reception. Cleared by software to disable reception.
TB80: The 9^th transmitted data bit in modes 2 and 3. Set or cleared by the CPU
depending on the function it performs such as parity check, multiprocessor
communication etc.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
39
Ver.G SM59R02G1 09/2015