SM59R02G1 Datasheet, PDF (30/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
6. Timer 0 and Timer 1
The SM59R02G1 has three 16-bit timer/counter registers: Timer 0, Timer 1 and Timer 2. All can be configured for counter
or timer operations.
In timer mode, the Timer 0 register or Timer 1 register is incremented every 1/12/96 machine cycles, which means that it
counts up after every 1/12/96 periods of the clk signal. It’s dependent on SFR(PFCON).
In counter mode, the register is incremented when the falling edge is observed at the corresponding input pin T0or T1.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator
frequency. There are no restrictions on the duty cycle, however to ensure proper recognition of 0 or 1 state, an input
should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1. Two Special Function registers (TMOD and TCON) are
used to select the appropriate mode.
Mnemonic Description
Direct
TL0
Timer 0 , low byte 8Ah
TH0
Timer 0 , high
byte
8Ch
TL1
Timer 1 , low byte 8Bh
TH1
Timer 1 , high
byte
8Dh
TMOD
Timer Mode
Control
89h
TCON
Timer/Counter
Control
88h
Peripheral
PFCON Frequency control D9h
register
Bit 7
GATE
TF1
Bit 6 Bit 5
Timer 0 and 1
C/T
M1
TR1 TF0
Bit 4 Bit 3
TL0[7:0]
TH0[7:0]
TL1[7:0]
TH1[7:0]
M0 GATE
TR0 IE1
Bit 2
C/T
IT1
S0RELPS[1:0]
T1PS[1:0]
Bit 1 Bit 0 RESET
00h
00h
00h
00h
M1
M0
00h
IE0
IT0
00h
T0PS[1:0]
00H
6.1. Timer/counter mode control register (TMOD)
Mnemonic: TMOD
7
6
5
GATE C/T
M1
Timer 1
Address: 89h
4
3
2
1
0 Reset
M0 GATE C/T
M1
M0 00h
Timer 0
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1,
respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON
register), a counter is incremented every falling edge on T0 or T1 input pin
C/T: Selects Timer or Counter operation. When set to 1, a counter operation is
performed, when cleared to 0, the corresponding register will function as a
timer.
M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1.
M1 M0 Mode
Function
00
Mode0 13-bit counter/timer, with 5 lower bits in TL0 or
TL1 register and 8 bits in TH0 or TH1 register
(for Timer 0 and Timer 1, respectively). The 3
high order bits of TL0 and TL1 are hold at zero.
01
Mode1 16-bit counter/timer.
10
Mode2 8 -bit auto-reload counter/timer. The reload
value is kept in TH0 or TH1, while TL0 or TL1 is
incremented every machine cycle. When TLx
overflows, a value from THx is copied to TLx.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
30
Ver.G SM59R02G1 09/2015