SM59R02G1 Datasheet, PDF (46/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
10. Interrupt
The SM59R02G1 provides 7 interrupt sources with four priority levels. Each source has its own request flag(s) located in
a special function register. Each interrupt requested by the corresponding flag could individually be enabled or disabled
by the enable bits in SFR’s IEN0, IEN1 and IEN2.
When the interrupt occurs, the engine will vector to the predetermined address as shown in Table 10.1. Once interrupt
service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a return
from instruction RETI. When an RETI is performed, the processor will return to the instruction that would have been next
when interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of
whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per machine cycle, and then samples are
polled by hardware. If the sample indicates a pending interrupt when the interrupt is enabled, then interrupt request flag is
set. On the next instruction cycle the interrupt will be acknowledged by hardware forcing an LCALL to appropriate vector
address.
Interrupt response will require a varying amount of time depending on the state of microcontroller when the interrupt
occurs. If microcontroller is performing an interrupt service with equal or greater priority, the new interrupt will not be
invoked. In other cases, the response time depends on current instruction. The fastest possible response to an interrupt is
7 machine cycles. This includes one machine cycle for detecting the interrupt and six cycles for perform the LCALL.
Table 10-1: Interrupt vectors
Interrupt Request Flags
Interrupt Vector
Address
IE0 – External interrupt 0
0003h
TF0 – Timer 0 interrupt
000Bh
IE1 – External interrupt 1
0013h
TF1 – Timer 1 interrupt
001Bh
RI0/TI0 – Serial channel 0 interrupt
0023h
TF2/EXF2 – Timer 2 interrupt
002Bh
WDT interrupt
008Bh
Interrupt Number
*(use Keil C Tool)
0
1
2
3
4
5
17
*See Keil C about C51 User’s Guide about Interrupt Function description
Mnemonic Description
IEN0
IEN1
IRCON
IEN2
IRCON2
IP0
IP1
Interrupt Enable
0 register
Interrupt Enable
1 register
Interrupt request
register
Interrupt Enable
2 register
Interrupt request
register 2
Interrupt priority
level 0
Interrupt priority
level 1
Direct
A8h
B8h
C0H
9AH
97H
A9h
B9h
Bit 7
EA
EXEN
2
EXF2
-
-
-
-
Bit 6 Bit 5
Interrupt
-
ET2
-
-
TF2
-
-
-
-
-
-
IP0.5
-
IP1.5
Bit 4
ES0
-
-
-
-
IP0.4
IP1.4
Bit 3
ET1
-
-
-
-
IP0.3
IP1.3
Bit 2
EX1
-
-
-
-
IP0.2
IP1.2
Bit 1
ET0
-
-
IEWD
T
WDTI
F
IP0.1
IP1.1
Bit 0 RESET
EX0
00h
-
00h
-
00h
-
00h
-
00h
IP0.0 00h
IP1.0 00h
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
46
Ver.G SM59R02G1 09/2015