SM59R02G1 Datasheet, PDF (28/57 Pages) SyncMOS Technologies,Inc – Instruction-set compatible with MCS-51

SM59R02G1
8-Bit Micro-controller
8KB with ISP Flash
& 256B RAM embedded
5. GPIO
The SM59R02G1 has six I/O ports: Port 0, Port 1, Port 2, Port 3, Port 4, and Port 5. Ports 0, 1, 2, 3, 4 are 8-bit ports and
Port 5 is a 2-bit port (Only Bit 4 and Bit 5). These are: quasi-bidirectional (standard 8051 port outputs), push-pull, open
drain, and input-only. Two configuration registers for each port select the output type for each port pin. All I/O port pins on
the SM59R02G1 may be configured by software to one of four types on a pin-by-pin basis, shown as below:
Mnemonic
Description
P0M0
P0M1
P1M0
P1M1
P2M0
P2M1
P3M0
P3M1
P4M0
P4M1
P5M0
P5M1
Port 0 output mode 0
Port 0 output mode 1
Port 1 output mode 0
Port 1 output mode 1
Port 2 output mode 0
Port 2 output mode 1
Port 3 output mode 0
Port 3 output mode 1
Port 4 output mode 0
Port 4 output mode 1
Port 5 output mode 0
Port 5 output mode 1
Direct
D2h
D3h
D4h
D5h
D6h
D7h
DAh
DBh
DCh
DDh
DEh
DFh
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
I/O port function register
P0M0 [7:0]
P0M1[7:0]
P1M0[7:0]
P1M1[7:0]
P2M0[7:0]
P2M1[7:0]
P3M0[7:0]
P3M1[7:0]
P4M0[7:0]
P4M1[7:0]
-
-
P5M0[5:4]
-
-
-
P5M1[5:4]
-
Bit 2
-
-
Bit 1
-
-
Bit 0
-
-
RESET
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
PxM1.y
0
0
1
1
PxM0.y
0
1
0
1
Port output mode
Quasi-bidirectional (standard 8051 port outputs) (pull-up)
Push-pull
Input only (high-impedance)
Open drain
The XTAL2 and XTAL1 can define as P5.4 and P5.5 by writer or ISP. When user use external OSC as system clock and
input into XTAL1, only XTAL2 can be defined as P5.4.
For general-purpose applications, every pin can be assigned to either high or low independently as given below:
Mnemonic Description
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Port 5
Port 4
Port 3
Port 2
Port 1
Port 0
Direct
D8h
E8h
B0h
A0h
90h
80h
Bit 7
-
P4.7
P3.7
P2.7
P1.7
P0.7
Bit 6
-
P4.6
P3.6
P2.6
P1.6
P0.6
Bit 5
Ports
P5.5
P4.5
P3.5
P2.5
P1.5
P0.5
Bit 4
P5.4
P4.4
P3.4
P2.4
P1.4
P0.4
Bit 3
-
P4.3
P3.3
P2.3
P1.3
P0.3
Bit 2
-
P4.2
P3.2
P2.2
P1.2
P0.2
Bit 1
-
P4.1
P3.1
P2.1
P1.1
P0.1
Bit 0 RESET
-
FFh
P4.0 FFh
P3.0 FFh
P2.0 FFh
P1.0 FFh
P0.0 FFh
Mnemonic: P0
7
6
P0.7 P0.6
5
P0.5
4
P0.4
3
P0.3
2
P0.2
1
P0.1
Address: 80h
0 Reset
P0.0 FFh
P0.7~ 0: Port0 [7] ~ Port0 [0]
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M061
28
Ver.G SM59R02G1 09/2015