M36W0R6030T0 Datasheet, PDF (9/26 Pages) STMicroelectronics – 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package

M36W0R6030T0, M36W0R6030B0
Table 2. Main Operating Modes
Operation
E_F G_F W_F L_F RP_{F WAITF(4)} E1_S E2_S G_S W_S UB_S LB_S DQ15-DQ0
Flash Read
V_IL V_IL V_{IH VIL(2)} V_IH
Flash Data Out
Flash Write
Flash Address
Latch
V_IL V_IH V_{IL VIL(2)} V_IH
V_IL X V_IH V_IL V_IH
SRAM must be disabled
Flash Data In
Flash Data Out
or Hi-Z ⁽³⁾
Flash Output
Disable
V_IL V_IH V_IH X V_IH
Flash Standby VIH X X X VIH
Hi-Z
Any SRAM mode is allowed
Flash Hi-Z
Flash Hi-Z
Flash Reset
XXX
X VIL
Hi-Z
Flash Hi-Z
SRAM Read
SRAM Write
Flash memory must be disabled
V_IL V_IH V_IL V_IH V_IL V_IL SRAM data out
V_IL V_IH X V_IL V_IL V_IL SRAM data in
Output Disable
V_IL V_IH V_IH V_IH V_IL V_IL SRAM Hi-Z
SRAM Standby
Any Flash mode is allowed.
V_IH X X X X X
X VIL X X X X
SRAM Hi-Z
SRAM Hi-Z
Note: 1. X = Don't care.
2. L_F can be tied to V_IH if the valid address has been previously latched.
3. Depends on G_F.
4. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064FT/B datasheet for details.
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