M36W0R6030T0 Datasheet, PDF (6/26 Pages) STMicroelectronics – 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package

M36W0R6030T0, M36W0R6030B0
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram and Table 1., Signal
Names, for a brief overview of the signals connect-
ed to this device.
Address Inputs (A0-A21). Addresses A0-A18
are common inputs for the Flash memory and the
SRAM components. The other lines (A19-A21) are
inputs for the Flash memory component only.
The Address Inputs select the cells in the memory
array to access during Bus Read operations. Dur-
ing Bus Write operations they control the com-
mands sent to the Command Interface of the Flash
memory Program/Erase Controller or they select
the cells to access in the SRAM.
The Flash memory is accessed through the Chip
Enable signal (E_F) and through the Write Enable
(W_F) signal, while the SRAM is accessed through
two Chip Enable signals (E1_S and E2_S) and the
Write Enable signal (W_S).
Data Input/Output (DQ0-DQ15). The Data I/O
outputs the data stored at the selected address
during a Bus Read operation or inputs a command
or the data to be programmed during a Write Bus
operation.
Flash Chip Enable (E_F). The Chip Enable in-
puts activate the memory control logics, input buff-
ers, decoders and sense amplifiers. When Chip
Enable is Low, V_IL, and Reset is High, V_IH, the de-
vice is in active mode. When Chip Enable is at V_IH
the Flash memory is deselected, the outputs are
high impedance and the power consumption is re-
duced to the standby level.
Flash Output Enable (G_F). The Output Enable
pin controls data outputs during Flash memory
Bus Read operations.
Flash Write Enable (W_F). The Write Enable
controls the Bus Write operation of the Flash
memories’ Command Interface. The data and ad-
dress inputs are latched on the rising edge of Chip
Enable or Write Enable whichever occurs first.
Flash Write Protect (WP_F). Write Protect is an
input that gives an additional hardware protection
for each block. When Write Protect is Low, V_IL,
Lock-Down is enabled and the protection status of
the Locked-Down blocks cannot be changed.
When Write Protect is at High, V_IH, Lock-Down is
disabled and the Locked-Down blocks can be
locked or unlocked. (Refer to Lock Status Table in
M58WR064FT/B datasheet).
Flash Reset (RP_F). The Reset input provides a
hardware reset of the memory. When Reset is at
V_IL, the memory is in Reset mode: the outputs are
high impedance and the current consumption is
reduced to the Reset Supply Current I_DD2. Refer to
Table 6., Flash Memory DC Characteristics - Cur-
rents for the value of I_DD2. After Reset all blocks
are in the Locked state and the Configuration Reg-
ister is reset. When Reset is at V_IH, the device is in
normal operation. Exiting Reset mode the device
enters Asynchronous Read mode, but a negative
transition of Chip Enable or Latch Enable is re-
quired to ensure valid data outputs.
The Reset pin can be interfaced with 3V logic with-
out any additional circuitry. It can be tied to V_RPH
(refer to Table 7., Flash Memory DC Characteris-
tics - Voltages).
Flash Latch Enable (L_F). Latch Enable latches
the address bits on its rising edge. The address
latch is transparent when Latch Enable is Low, V_IL,
and it is inhibited when Latch Enable is High, V_IH.
Latch Enable can be kept Low (also at board level)
when the Latch Enable function is not required or
supported.
Flash Clock (K_F). The Clock input synchronizes
the Flash memory to the microcontroller during
synchronous read operations; the address is
latched on a Clock edge (rising or falling, accord-
ing to the configuration settings) when Latch En-
able is at V_IL. Clock is don't care during
Asynchronous Read and in write operations.
Flash Wait (WAIT_F). WAIT is a Flash output sig-
nal used during Synchronous Read to indicate
whether the data on the output bus are valid. This
output is high impedance when Flash Chip Enable
is at V_IH or Flash Reset is at V_IL. It can be config-
ured to be active during the wait cycle or one clock
cycle in advance. The WAIT_F signal is not gated
by Output Enable.
SRAM Chip Enable inputs (E1_S, E2_S). The
Chip Enable inputs activate the SRAM memory
control logic, input buffers and decoders. E1_S at
V_IH with E2_S at V_IH deselects the memory, reduc-
ing the power consumption to the standby level,
whereas E2_S at V_IL deselects the memory and re-
duces the power consumption to the Power-down
level, regardless of the level of E1_S. E1_S and E2_S
can also be used to control writing to the SRAM
memory array, while W_S remains at V_IL. It is not al-
lowed to set E_F at V_IL, E1_S at V_IL and E2_S at V_IH at
the same time.
SRAM Write Enable (W_S). The Write Enable in-
put controls writing to the SRAM memory array.
W_S is active low.
SRAM Output Enable (G_S). The Output Enable
gates the outputs through the data buffers during
a Read operation of the SRAM memory. G_S is ac-
tive low.
SRAM Upper Byte Enable (UB_S). The Upper
Byte Enable input enables the upper byte for
SRAM (DQ8-DQ15). UB_S is active low.
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