M36W0R6030T0 Datasheet, PDF (4/26 Pages) STMicroelectronics – 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package

M36W0R6030T0, M36W0R6030B0
SUMMARY DESCRIPTION
The M36W0R6030T0 and M36W0R6030B0 com-
bine two memory devices in a Multi-Chip Package:
a 64-Mbit, Multiple Bank Flash memory, the
M58WR064FT/B, and an 8-Mbit SRAM. Recom-
mended operating conditions do not allow more
than one memory to be active at the same time.
The memory is offered in a Stacked TFBGA88
(8 x 10mm, 8x10 ball array, 0.8mm pitch) pack-
age.
In addition to the standard version, the packages
are also available in Lead-free version, in compli-
ance with JEDEC Std J-STD-020B, the ST ECO-
PACK 7191395 Specification, and the RoHS
(Restriction of Hazardous Substances) directive.
All packages are compliant with Lead-free solder-
ing processes.
is supplied with all the bits erased (set to ‘1’).
Figure 2. Logic Diagram
V_DDQ
V_DDF
V_PPF
V_DDS
22
A0-A21
E_F
G_F
W_F
RP_F
WP_F
L_F
K_F
16
DQ0-DQ15
WAIT_F
M36W0R6030T
M36W0R6030B
E1_S
G_S
W_S
E2_S
UB_S
LB_S
Table 1. Signal Names
A0-A21 ⁽¹⁾
Address Inputs
DQ0-DQ15 Common Data Input/Output
V_DDF
Flash Memory Power Supply
V_DDQ
Common Flash and SRAM Power
Supply for I/O Buffers
V_PPF
Common Flash Optional Supply
Voltage for Fast Program and Erase
V_SS
Ground
V_DDS
SRAM Power Supply
NC
Not Connected Internally
DU
Do Not Use as Internally Connected
Flash Memory Signals
L_F
Latch Enable input
E_F
Chip Enable input
G_F
Output Enable input
W_F
Write Enable input
RP_F
Reset input
WP_F
Write Protect input
K_F
Burst Clock
WAIT_F
Wait Data in Burst Mode
SRAM Signals
E1_S, E2_S
Chip Enable input
G_S
Output Enable input
W_S
Write Enable input
UB_S
Upper Byte Enable input
LB_S
Lower Byte Enable input
Note: 1. A21-A19 are not connected to the SRAM component.
VSS
AI08534C
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