M36W0R6030T0 Datasheet, PDF (11/26 Pages) STMicroelectronics – 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package

M36W0R6030T0, M36W0R6030B0
SRAM OPERATIONS
There are five standard operations that control the
device. These are Read, Write, Standby/Power-
down, Data Retention and Output Disable.
Read. Read operations are used to output the
contents of the SRAM Array.
The device is in Byte Read mode whenever Write
Enable, W_S, is at V_IH, Output Enable, G_S, is at V_IL,
Chip Enable, E1_S, is at V_IL, Chip Enable, E2_S, is at
V_IH, and UB_S or LB_S is at V_IL.
The device is in Word Read mode whenever Write
Enable, W_S, is at V_IH, Output Enable, G_S, is at V_IL,
Byte Enable inputs UB_S and LB_S are both at V_IL
and the two Chip Enable inputs, E1_S, and E2_S are
Don’t Care.
The Read and Standby AC Waveforms are shown
in Figures 9 and 10, respectively and the parame-
ters are given in Table 9., Read AC Characteris-
tics.
Write. Write operations are used to write data to
the SRAM. The device is in Write mode whenever
W_S, E1_S and UB_S and/or LB_S are at V_IL, and E2_S
is at V_IH. All these signals must be asserted to ini-
tiate a Write cycle. The data is latched on the fall-
ing edge of E1_S, the rising edge of E2_S, the falling
edge of W_S, or the falling edge of UB_S and/or LB_S,
whichever occurs last. The Write cycle will termi-
nate on the rising edge of E1_S, the rising edge of
W_S, the rising edge of UB_S and/or LB_S, or the fall-
ing edge of E2_S, whichever occurs first. The tim-
ings are referenced to the signal that terminates
the Write cycle.
The outputs are disabled during Write cycles
(whenever E1_S, at V_IL, E2_S at V_IH, and W_S at V_IL).
The Write AC Waveforms are shown in Figures
11, 12, 13 and 14, while Table 10. gives the Write
AC Characteristics.
Standby/Power-Down. The device automatically
enters the Standby/Power-Down mode when
DQ0-DQ15 are not toggling, reducing the power
consumption to the Standby level, I_SB.
The device is also in Standby/Power-Down mode
whenever E1_S is at V_IH, E2_S is at V_IL or both UB_S
and LB_S are at V_IH. The outputs then become high
impedance.
The Standby AC Waveforms are shown in Figure
10. See Table 9., Read AC Characteristics, for
timings.
Data Retention. The data retention mode is en-
tered t_CDR after de-asserting E1_S, E2_S or UB_S and
LB_S. The data retention performance as V_DD goes
down to V_DR is described in Table 11., Figures 15
and 16, SRAM Low V_DD Data Retention AC Wave-
forms, E1_S or UB_S / LB_S Controlled and SRAM
Low V_DD Data Retention AC Waveforms, E2_S
Controlled, respectively.
Output Disable. The device is in the Output Dis-
able mode whenever G_S, is at V_IH. In this mode,
DQ0-DQ15 are high impedance.
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