M36W0R6030T0 Datasheet, PDF(20/26 Page) STMicroelectronics – 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package

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M36W0R6030T0 Datasheet, PDF (20/26 Pages) STMicroelectronics – 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package

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M36W0R6030T0, M36W0R6030B0

Figure 13. Write AC Waveforms, WS Controlled with GS Low

A0-A18

E1S

tAVAV

VALID

tAVWH

tE1LWH

tE2HWH

tWHAX

E2S

UBS, LBS

DQ0-DQ15

tAVWL

tWLDZ

Note 1

tBLWH

tWLWH

tDVWH

tWHDX

tWHDZ

INPUT VALID

Note: 1. During this period, the I/O pins are in output mode and input signals should not be applied.

2. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

3. UBS, LBS means both UBS and LBS.

Figure 14. Write AC Waveform, UBS and LBS Controlled GS Low

tAVAV

A0-A18

VALID

tAVBH

tE1LBH

tE2HBH

E1S

AI08195B

E2S

UBS, LBS

DQ0-DQ15

tAVBL

Note 2

tBLBH

tBHAX

tWLBH

tDVBH

tBHDX

INPUT VALID

Note: 1. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

2. The I/O pins are in output mode and input signals should not be applied.

3. UBS, LBS means both UBS and LBS.

AI08196B

20/26

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