M36W0R6030T0 Datasheet, PDF (22/26 Pages) STMicroelectronics – 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package

M36W0R6030T0, M36W0R6030B0
Figure 15. SRAM Low V_DD Data Retention AC Waveforms, E1_S or UB_S / LB_S Controlled
V_DDS
E1_S or UB_S, LB_S
V_{DDS (min)}
DATA RETENTION MODE
V_DR
tCDR
tR
V_{DDS (min)}
AI08197B
Figure 16. SRAM Low V_DD Data Retention AC Waveforms, E2_S Controlled
V_DDS
E2_S
V_{DDS (min)}
DATA RETENTION MODE
V_DR
tCDR
tR
V_{DDS (min)}
AI08198B
Table 11. SRAM Low V_DD Data Retention Characteristic
Symbol
Parameter
Test Condition
I_DDDR
Supply Current
(Data Retention)
V_DDS = 1.0V, E1_S ≥ V_DDS – 0.2V
or E2_S ≤ 0.2V,
V_IN ≥ V_DDS – 0.2V or V_IN ≤ 0.2V
V_DR
Supply Voltage
(Data Retention)
t_CDR Chip Disable to Power Down
t_R
Operation Recovery Time
Note: 1. Sampled only. Not 100% tested.
Min Max Unit
10 µA
1.0
V
0
ns
70
ns
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