M36W0R6030T0 Datasheet, PDF(19/26 Page) STMicroelectronics – 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package

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M36W0R6030T0 Datasheet, PDF (19/26 Pages) STMicroelectronics – 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package

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M36W0R6030T0, M36W0R6030B0

Figure 12. Write AC Waveforms, WS Controlled, GS High during Write

tAVAV

A0-A18

VALID

tAVWH

tE1LWH

E1S

tWHAX

E2S

UBS, LBS

tAVWL

tE2HWH

tWLWH

tBLWH

DQ0-DQ15

tGHDX

Note 2

tDVWH

tWHDX

INPUT VALID

Note: 1. WS, E1S, E2S and UBS,LBS must be asserted to initiate a write cycle.

2. The I/O pins are in output mode and input signals should not be applied.

3. If E1S, E2S and WS are deasserted at the same time, DQ0-DQ15 remain high impedance.

4. UBS, LBS means both UBS and LBS.

AI08194B

19/26

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