M36W0R6030T0 Datasheet, PDF (8/26 Pages) STMicroelectronics – 64 Mbit (4Mb x16, Multiple Bank, Burst) Flash Memory and 8 Mbit (512Kb x16) SRAM, Multi-Chip Package

M36W0R6030T0, M36W0R6030B0
FUNCTIONAL DESCRIPTION
The Flash memory and SRAM components have
separate power supplies but share the same
grounds. They are distinguished by three Chip En-
able inputs: E_F for the Flash memory and E1_S and
E2_S for the SRAM.
Recommended operating conditions do not allow
more than one device to be active at a time. The
most common example is simultaneous read oper-
ations on one of the Flash and the SRAM which
would result in a data bus contention. Therefore it
is recommended to put the other devices in the
high impedance state when reading the selected
device.
Figure 4. Functional Block Diagram
V_DDF V_PPF V_DDQ
A19-A21
A0-A18
E_F
G_F
W_F
L_F
K_F
RP_F
WP_F
64 Mbit
Flash
Memory
WAIT_F
DQ0-DQ15
V_DDS
8/26
E1_S
G_S
W_S
E2_S
UB_S
LB_S
8 Mbit SRAM
V_SS
AI08536C