M36DR432AD Datasheet, PDF (42/52 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product

M36DR432AD, M36DR432BD
Table 24. SRAM Write AC Characteristics
SRAM
Symbol
Alt
Parameter
70
Unit
Min
Max
t_AVAV
t_WC
Write Cycle Time
70
ns
t_AVEL
t_AS ⁽¹⁾ Address Valid to Chip Enable Low
0
ns
t_AVWH
t_AW
Address Valid to Write Enable High
60
ns
t_AVWL
t_AS ⁽¹⁾ Address Valid to Write Enable Low
0
ns
t_BLWH
t_BW
UBS, LBS Valid to End of Write
60
ns
t_DVWH
t_DW
Input Valid to Write Enable High
30
ns
t_EHAX
t_WR ⁽²⁾ Chip Enable High to Address Transition
0
ns
t_ELWH,
t_CW ⁽³⁾ Chip Select to End of Write
60
ns
t_WHAX
t_WR ⁽²⁾ Write Enable High to Address Transition
0
ns
t_WHDX
t_DH
Write Enable High to Input Transition
0
ns
t_WHQX
t_OW
Write Enable High to Output Transition
10
ns
t_WLQZ
t_WHZ Write Enable Low to Output Hi-Z
25
ns
t_WLWH
t_WP ⁽⁴⁾ Write Enable Pulse Width
50
ns
Note: 1. tAS is measured from the address valid to the beginning of write.
2. t_WR is measured from the end or write to the address change. t_WR applied in case a write ends as ES or WS goes High.
3. tCW is measured from ES going Low end of write.
4. A Write occurs during the overlap (t_WP) of Low ES and Low WS. A write begins when ES goes Low and WS goes Low with asserting
UBS or LBS for single byte operation or simultaneously asserting UBS and LBS for double byte operation. A write ends at the ear-
liest transition when ES goes High and WS goes High. The t_WP is measured from the beginning of write to the end of write.
Figure 24. SRAM Low V_DDS Data Retention AC Waveforms, ES Controlled
VDDS 1.65 V
VDR ≥ 1.0 V
tCDR
DATA RETENTION MODE
tR
ES
ES ≥ VDDS – 0.2V
AI07325
42/52