M36DR432AD Datasheet, PDF (24/52 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product

M36DR432AD, M36DR432BD
SRAM COMPONENT
The SRAM is a 4 Mbit (256Kb x16) low-power con-
sumption memory array with low V_DDS data reten-
tion.
SRAM Operations
The following operations can be performed using
the appropriate bus cycles: Read Array, Write Ar-
ray, Output Disable, Power Down (see Table 2).
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable (WS) is at V_IH with
Output Enable (GS) at V_IL, Chip Enable ES and
UBS, LBS combinations are asserted.
Valid data will be available at the output pins within
t_AVQV after the last stable address, provided that
GS is Low and ES is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (t_ELQV or
t_GLQV) rather than the address. Data out may be
indeterminate at t_ELQX and t_GLQX, but data lines
will always be valid at t_AVQV (see Table 23, Figures
17 and 18).
Write. Write operations are used to write data in
the SRAM. The SRAM is in Write mode whenever
the WS and ES pins are at V_IL. Either the Chip En-
able input (ES) or the Write Enable input (WS)
must be de-asserted during address transitions for
subsequent write cycles. Write begins with the
concurrence of Chip Enable being active and WS
at V_IL. A Write begins at the latest transition
among ES going to V_IL and WS going to V_IL.
Therefore, address setup time is referenced to
Write Enable and Chip Enable as t_AVWL and t_AVEL
respectively, and is determined by the latter occur-
ring edge. The Write cycle can be terminated by
the rising edge of ES or the rising edge of WS,
whichever occurs first.
If the Output is enabled (ES=V_IL and GS=V_IL),
then WS will return the outputs to high impedance
within t_WLQZ of its falling edge. Care must be taken
to avoid bus contention in this type of operation.
Data input must be valid for t_DVWH before the ris-
ing edge of Write Enable, or for t_DVEH before the
rising edge of ES, whichever occurs first, and re-
main valid for t_WHDX and t_EHAX (see Table 24, Fig-
ure 20, 22, 24).
Standby/Power-Down. The SRAM chip has a
Chip Enable power-down feature which invokes
an automatic standby mode (see Table 23, Figure
19) whenever either Chip Enable is de-asserted
(ES=V_IH).
Data Retention. The SRAM data retention per-
formances as V_DDS go down to V_DR are described
in Table 25 and Figure 24. In ES controlled data
retention mode, minimum standby current mode is
entered when ES ≥ V_DDS – 0.2V.
Output Disable. The data outputs are high im-
pedance when the Output Enable (GS) is at V_IH
with Write Enable (WS) at V_IH.
24/52