M36DR432AD Datasheet, PDF (13/52 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product

M36DR432AD, M36DR432BD
Figure 5. Flash Security Block and Protection Register Memory Map
SECURITY BLOCK
Parameter Block # 0
PROTECTION REGISTER
88h
User Programmable OTP
85h
84h
Unique device number
81h
80h
Protection Register Lock
210
Flash Bus Operations
The following operations can be performed using
the appropriate bus cycles: Flash Read Array
(Random and Page Modes), Flash Write, Flash
Output Disable, Flash Standby and Flash Reset/
Power-Down, see Table 2, Main Operation
Modes.
Flash Read. Flash Read operations are used to
output the contents of the Memory Array, the Elec-
tronic Signature, the Status Register, the CFI, the
Block Protection Status or the Configuration Reg-
ister status. Read operation of the Flash memory
array is performed in asynchronous page mode,
that provides fast access time. Data is internally
read and stored in a page buffer. The page has a
size of 4 words and is addressed by A0-A1 ad-
dress inputs. Read operations of the Electronic
Signature, the Status Register, the CFI, the Block
Protection Status, the Configuration Register sta-
tus and the Security Code are performed as single
asynchronous read cycles (Random Read). Both
Flash Chip Enable EF and Flash Output Enable
GF must be at V_IL in order to read the output of the
memory.
Flash Write. Write operations are used to give
commands to the memory or to latch Input Data to
be programmed. A write operation is initiated
when Chip Enable EF and Write Enable WF are at
V_IL with Output Enable GF at V_IH. Addresses are
latched on the falling edge of WF or EF whichever
occurs last. Commands and Input Data are
latched on the rising edge of WF or EF whichever
occurs first. Noise pulses of less than 5ns typical
on EF, WF and GF signals do not start a write cy-
cle.
AI06185
Flash Output Disable. The data outputs are high
impedance when the Output Enable GF is at V_IH
with Write Enable WF at V_IH.
Flash Standby. The memory is in standby when
Chip Enable EF is at V_IH and the P/E.C. is idle.
The power consumption is reduced to the standby
level and the outputs are high impedance, inde-
pendent of the Output Enable GF or Write Enable
WF inputs.
Automatic Flash Standby. In Read mode, after
150ns of bus inactivity and when CMOS levels are
driving the addresses, the chip automatically en-
ters a pseudo-standby mode where consumption
is reduced to the CMOS standby value, while out-
puts still drive the bus.
Flash Power-Down. The memory is in Power-
Down when the Configuration Register is set for/
Power-Down and RPF is at V_IL. The power con-
sumption is reduced to the Power-Down level, and
Outputs are high impedance, independent of the
Chip Enable EF, Output Enable GF or Write En-
able WF inputs.
Dual Bank Operations. The Dual Bank allows
data to be read from one bank of memory while a
program or erase operation is in progress in the
other bank of the memory. Read and Write cycles
can be initiated for simultaneous operations in dif-
ferent banks without any delay. Status Register
during Program or Erase must be monitored using
an address within the bank being modified.
Flash Command Interface
All Bus Write operations to the memory are inter-
preted by the Command Interface. Commands
consist of one or more sequential Bus Write oper-
ations. An internal Program/Erase Controller han-
13/52