M36DR432AD Datasheet, PDF (23/52 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product

M36DR432AD, M36DR432BD
Table 12. Status Register Bits
DQ
Name
Logic Level
Definition
Note
’1’
Erase complete or erase block
in Erase Suspend.
7
Data
Polling
’0’
Erase in progress
Indicates the P/E.C. status, check
during Program or Erase, and on
Program complete or data of
completion before checking bits DQ5
DQ
non erase block during Erase _{for Program or Erase success.}
Suspend.
DQ
Program in progress⁽²⁾
6 Toggle Bit
’-1-0-1-0-1-0-1-’
DQ
’-1-1-1-1-1-1-1-’
Erase or Program in progress
Program complete
Erase complete or Erase
Suspend on currently addressed
block
Successive reads output
complementary data on DQ6 while
Programming or Erase operations are
in progress. DQ6 remains at constant
level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
5 Error Bit
’1’
Program or Erase Error
This bit is set to ’1’ in the case of
’0’
Program or Erase in progress ^{Programming or Erase failure.}
4 Reserved
3
Erase Time
Bit
P/E.C. Erase operation has started.
’1’
Erase Timeout Period Expired Only possible command entry is Erase
Suspend
An additional block to be erased in
’0’
Erase Timeout Period in
progress
parallel can be entered to the P/E.C
provided that it belongs to the same
bank
2 Toggle Bit
’-1-0-1-0-1-0-1-’
1
Erase Suspend read in the
Erase Suspended Block.
Erase Error due to the currently
addressed block (when DQ5 =
’1’).
Program in progress or Erase
complete.
Indicates the erase status and allows
to identify the erased block.
DQ
Erase Suspend read on non
Erase Suspend block.
1 Reserved
0 Reserved
Note: 1. Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations.
2. In case of double word program DQ7 refers to the last word input.
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