M36DR432AD Datasheet, PDF (12/52 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product

M36DR432AD, M36DR432BD
FLASH MEMORY COMPONENT
The Flash Memory is a 32 Mbit (2Mbit x16) non-
volatile Flash memory that may be erased electri-
cally at block level and programmed in-system on
a Word-by-Word basis using a 1.65V to 2.2V V_DDF
supply for the circuitry and a 1.65V to 2.2V V_DDQF
supply for the Input/Output pins (in the stacked de-
vice, V_DDF and V_DDQF are tied internally). An op-
tional 12V V_PPF power supply is provided to speed
up customer programming.
The Flash device features an asymmetrical block
architecture with an array of 71 blocks divided into
two banks, Banks A and B, providing Dual Bank
operations. While programming or erasing in Bank
A, read operations are possible in Bank B or vice
versa. Only one bank at a time is allowed to be in
program or erase mode. The bank architecture is
summarized in Table 3, and the Block Addresses
are shown in Appendix A. The Parameter Blocks
are located at the top of the memory address
space for the M36DR432AD and, at the bottom for
the M36DR432BD.
Each block can be erased separately. Erase can
be suspended, in order to perform either read or
program in any other block, and then resumed.
Each block can be programmed and erased over
100,000 cycles.
Table 3. Flash Bank Architecture
Bank Size
Bank A
4 Mbits
Bank B
28 Mbits
Program and Erase commands are written to the
Command Interface of the memory. An internal
Program/Erase Controller takes care of the tim-
ings necessary for program and erase operations.
The end of a program or erase operation can be
detected and any error conditions identified in the
Status Register. The command set required to
control the memory is consistent with JEDEC stan-
dards.
The Flash memory features an instant, individual
block locking scheme that allows any block to be
locked or unlocked with no latency, enabling in-
stant code and data protection. All blocks have two
levels of protection. They can be individually
locked and locked-down preventing any acciden-
tal programming or erasure. All blocks are locked
at Power Up and Reset.
The device includes a 128 bit Protection Register
and a Security Block to increase the protection of
a system’s design. The Protection Register is di-
vided into two 64 bit segments. The first segment
contains a unique device number written by ST,
while the second one is one-time-programmable
by the user. The user programmable segment can
be permanently protected. The Security Block, pa-
rameter block 0, can be permanently protected by
the user. Figure 5, shows the Flash Security Block
and Protection Register Memory Map.
Parameter Blocks
8 blocks of 4 KWords
-
Main Blocks
7 blocks of 32 KWords
56 blocks of 32 KWords
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