M36DR432AD Datasheet, PDF(14/52 Page) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product

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M36DR432AD Datasheet, PDF (14/52 Pages) STMicroelectronics – 32 Mbit 2Mb x16, Dual Bank, Page Flash Memory and 4 Mbit 256Kb x16 SRAM, Multiple Memory Product

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M36DR432AD, M36DR432BD

dles all timings and verifies the correct execution

of the Program and Erase commands. Two bus

write cycles are required to unlock the Command

Interface. They are followed by a setup or confirm

cycle. The increased number of write cycles is to

ensure maximum data security.

The Program/Erase Controller provides a Status

monitor the progress or the result of the operation.

The Command Interface is reset to Read mode

when power is first applied or exiting from Reset.

Command sequences must be followed exactly.

Any invalid combination of commands will reset

the device to Read mode

Flash Read/Reset Command. The Read/Reset

command returns the device to Read mode. One

Bus Write cycle is required to issue the Read/Re-

set command and return the device to Read mode.

Subsequent Read operations will read the ad-

dressed location and output the data. The write cy-

cle can be preceded by the unlock cycles but it is

not mandatory.

Flash Read CFI Query Command. The Read

CFI Query command is used to read data from the

Common Flash Interface (CFI) and the Electronic

Signature (Manufacturer or the Device Code, see

Table 5). The Read CFI Query Command consists

of one Bus Write cycle. Once the command is is-

sued the device enters Read CFI mode. Subse-

quent Bus Read operations read the Common

Flash Interface or Electronic Signature. Once the

device has entered Read CFI mode, only the

Read/Reset command should be used and no oth-

er. Issuing the Read/Reset command returns the

device to Read mode.

See Appendix B, Common Flash Interface, Tables

33, 34, and 35 for details on the information con-

tained in the Common Flash Interface memory ar-

ea.

Auto Select Command. The Auto Select com-

mand uses the two unlock cycles followed by one

write cycle to any bank address to setup the com-

mand. Subsequent reads at any address will out-

put the Block Protection status, Protection

figuration Register status depending on the levels

of A0 and A1 (see Tables 6, 7 and 8). Once the

Auto Select command has been issued only the

Read/Reset command should be used and no oth-

er. Issuing the Read/Reset command returns the

device to Read mode.

Set Configuration Register Command. The

Flash component contains a Configuration Regis-

ter, see Table 7, Configuration Register.

It is used to define the status of the Reset/Power-

Down functions. The value for the Configuration

address bits are ignored. Address input A10 de-

fines the status of the Reset/Power-Down func-

tions. If it is set to â0â the Reset function is enabled,

if it is set to â1â the Power-Down function is en-

abled. At Power Up the Configuration Register bit

is set to â0â.

The Set Configuration Register command is used

to write a new value to the Configuration Register.

The command uses the two unlock cycles followed

by one write cycle to setup the command and a

further write cycle to write the data and confirm the

command.

Program Command. The Program command

uses the two unlock cycles followed by a write cy-

cle to setup the command and a further write cycle

to latch the Address and Data and start the Pro-

gram Erase Controller. Read operations within the

same bank output the Status Register after pro-

gramming has started.

Note that the Program command cannot change a

bit set at â0â back to â1â. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole bank from â0â to â1â. If the Program

command is used to try to set a bit from â0â to â1â

Status Register Error bit DQ5 will be set to â1â, only

if VPPF is in the range of 11.4V to 12.6V.

Double Word Program Command. This feature

is offered to improve the programming throughput

by writing a page of two adjacent words in parallel.

The VPPF supply voltage is required to be from

11.4V to 12.6V for the Double Word Program com-

mand.

The command uses the two unlock cycles followed

by a write cycle to setup the command. A further

two cycles are required to latch the address and

data of the two Words and start the Program Erase

Controller.

The addresses must be the same except for the

A0. The Double Word Program command can be

executed in Bypass mode to skip the two unlock

cycles.

Note that the Double Word Program command

cannot change a bit set at â0â back to â1â. One of the

Erase Commands must be used to set all the bits

in a block or in the whole bank from â0â to â1â. If the

Double Word Program command is used to try to

set a bit from â0â to â1â Status Register Error bit DQ5

will be set to â1â.

Quadruple Word Program Command. The

Quadruple Word Program command improves the

programming throughput by writing a page of four

adjacent words in parallel. The four words must

differ only for the addresses A0 and A1. The VPPF

supply voltage is required to be from 11.4V to

12.6V for the Quadruple Word Program com-

mand.

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