MB84VD2118XEM-70 Datasheet, PDF (8/52 Pages) SPANSION – Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS

MB84VD2118XEM/2119XEM-70
User Bus Operations Table (Flash=Byte mode; CIOf=VSS, SRAM=Byte mode; CIOs=VSS)
Operation *^1,*³
CEf CE1s CE2s DQ15/A–1 OE WE SA LB UB
DQ7 to
DQ0
DQ14 to
DQ8
WP/
RESET ACC
*⁵
Full Standby
HX
H
XL
X
X X X X X High-Z High-Z
H
X
X
H H X X X High-Z High-Z
HL H
X
X X X H H High-Z High-Z
Output Disable
H
X
HX
L
A–1 H H X X X High-Z High-Z
XL
Read from Flash
*²
L
H
X
X
L
A–1
LHX X X
DOUT High-Z
H
X
Write to Flash
HX
L
A–1
HLX X X
DIN
High-Z H
X
XL
Read from SRAM H L H
X
L H SA X X
DOUT High-Z
H
X
Write to SRAM H L H
X
X L SA X X
DIN
High-Z H
X
Temporary
Sector Group
XX X
X
XXX X X
X
Unprotection *⁴
X
VID
X
Flash Hardware
Reset
X
H
X
X
L
X
X X X X X High-Z High-Z L
X
Boot Block Sector
Write Protection
X
X
X
X
XXX X X
X
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
X
X
L
*1 : Other operations except for indicated this column are inhibited.
*2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4 : It is also used for the extended sector group protections.
*5 : WP/ACC = VIL; protection of boot sectors.
WP/ACC = VIH; removal of boot sectors protection.
WP/ACC = VACC (9 V); Program time will reduce by 40%.
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