MB84VD2118XEM-70 Datasheet, PDF (44/52 Pages) SPANSION – Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS

MB84VD2118XEM/2119XEM-70
• Write Cycle *³ (WE control) (SRAM)
Address
tAS
WE
CE1s
tWC
tWP
tWR
tAW
tCW
CE2s
LB, UB
DOUT
*1
DIN
*4
tCW
tBW
tODW
tOEW
*2
tDS
tDH
Valid Data In
*4
*1 : If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output will
remain at High-Z.
*2 : If CE1s goes “H” (or CE2s goes “L”) coincident with or before WE goes “H”, the output will
remain at High-Z.
*3 : If OE is “H” during the write cycle, the outputs will remain at High-Z.
*4 : Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
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