MB84VD2118XEM-70 Datasheet, PDF (27/52 Pages) SPANSION – Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM CMOS

MB84VD2118XEM/2119XEM-70
• Read Only Operations Characteristics (Flash)
Parameter
Symbol
JEDEC Standard
Test Setup
Read Cycle Time
tAVAV
tRC
—
Address to Output Delay
tAVQV
tACC
CEf = VIL
OE = VIL
Chip Enable to Output Delay
tELQV
tCEf OE = VIL
Output Enable to Output Delay
tGLQV
tOE
—
Chip Enable to Output High-Z
tEHQZ
tDF
—
Output Enable to Output High-Z
tGHQZ
tDF
—
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First
tAXQX
tOH
—
RESET Pin Low to Read Mode
—
tREADY
—
* : Test Conditions
Output Load : 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels : 0.0 V or 3.0 V
Timing measurement reference level
Input : 1.5 V
Output : 1.5 V
Value*
Unit
Min
Max
70
—
ns
—
70
ns
—
70
ns
—
30
ns
—
25
ns
—
25
ns
0
—
ns
—
20
µs
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